DSPIC30F3011-20E/ML Microchip Technology, DSPIC30F3011-20E/ML Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F3011-20E/ML
• Description: IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-20E/ML

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. Module: Interrupt Controller
EXAMPLE 5:
EXAMPLE 7:
© 2010 Microchip Technology Inc.
.include "p30fxxxx.inc"
...
DISI #4 ; protect the disable
; of INT1
BCLR IEC1, #INT1IE ; disable interrupt 1
... ; next instruction
;protected by DISI
// Note: Macros defined in device include files
#define SET_AND_SAVE_CPU_IPL (save_to, ipl){ \
save_to = SRbits.IPL; \
SET_CPU_IPL (ipl); } (void) 0;
#define RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to)
#include "p30fxxxx.h"
. . .
int save_to;
SET_AND_SAVE_CPU_IPL (save_to, 3)
. . .
RESTORE_CPU_IPL (save_to)
The following sequence of events will lead to an
address
“Interrupt 1” is used to represent any enabled
dsPIC30F interrupt.
1. User software performs one of the following
2. Interrupt 1 occurs between 2 and 4 instruction
Work arounds
Work around 1: For Assembly Language
Source Code
The user may disable interrupt nesting, disable
interrupts before modifying the Interrupt 1 set-
ting or execute a DISI instruction before modi-
fying the CPU IPL or Interrupt 1. A minimum
DISI value of 4 is required if the DISI instruction
is executed immediately before the CPU IPL or
Interrupt 1 is modified, as shown in Example 5.
It is necessary to have DISI active for four cycles
after the CPU IPL or Interrupt 1 is modified.
operations:
-
-
-
-
cycles after any of the operations listed above.
CPU IPL is raised to Interrupt 1 IPL
level or higher, or
Interrupt 1 IPL is lowered to CPU IPL
level or lower, or
Interrupt 1 is disabled (Interrupt 1 IE
bit set to ‘0’), or
Interrupt 1 flag is cleared
error
USING DISI
USING SET_AND_SAVE_CPU_IPL AND RESTORE_CPU_IPL MACROS
trap.
The
generic
term
EXAMPLE 6:
// Note: Macro defined in device include
// files
#define SET_CPU_IPL (ipl){ \
int DISI_save; \
\
DISI_save = DISICNT; \
asm volatile ("disi #0x3FFF");\
SRbits.IPL = ipl; \
__builtin_nop();
__builtin_nop();
DISICNT = DISI_save; } (void) 0;
#include "p30fxxxx.h"
. . .
SET_CPU_IPL (3)
. . .
Work around 2: For C Language Source Code
For applications using the C language, MPLAB
C30 versions 1.32 and higher provide several
macros for modifying the CPU IPL. The
SET_CPU_IPL macro provides the ability to
safely modify the CPU IPL, as shown in
Example 6.
There is one level of DISI, so this macro saves
and restores the DISI state. For temporarily
modifying and restoring the CPU IPL, the mac-
ros
RESTORE_CPU_IPL can be used, as shown in
Example 7. These macros also make use of the
SET_CPU_IPL macro.
dsPIC30F3010/3011
SET_AND_SAVE_CPU_IPL
USING SET_CPU_IPL
MACRO
\
\
DS80449D-page 7
and