DSPIC30F3010-20E/ML Microchip Technology, DSPIC30F3010-20E/ML Datasheet - Page 71
![IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3010-20E/ML
Manufacturer Part Number
DSPIC30F3010-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F3010-30ISO.pdf
(228 pages)
4.DSPIC30F3010-30ISO.pdf
(18 pages)
5.DSPIC30F3010-30ISO.pdf
(6 pages)
6.DSPIC30F3010-30ISO.pdf
(16 pages)
7.DSPIC30F3010-30ISO.pdf
(22 pages)
Specifications of DSPIC30F3010-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F3010-30ISO PDF datasheet #3
- DSPIC30F3010-30ISO PDF datasheet #4
- DSPIC30F3010-30ISO PDF datasheet #5
- DSPIC30F3010-30ISO PDF datasheet #6
- DSPIC30F3010-30ISO PDF datasheet #7
- Current page: 71 of 228
- Download datasheet (4Mb)
10.0
This section describes the 32-bit general purpose timer
module (Timer2/3) and associated operational modes.
Figure 10-1
32-bit Timer2/3 module.
show Timer2/3 configured as two independent 16-bit
timers; Timer2 and Timer3, respectively.
The Timer2/3 module is a 32-bit timer, which can be
configured as two 16-bit timers, with selectable
operating modes. These timers are utilized by other
peripheral modules such as:
• Input Capture
• Output Compare/Simple PWM
The following sections provide a detailed description,
including setup and control registers, along with
associated block diagrams for the operational modes of
the timers.
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer2 and
• Single 32-bit timer operation
• Single 32-bit synchronous counter
Further, the following operational characteristics are
supported:
• ADC Event Trigger
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
© 2010 Microchip Technology Inc.
Note:
Note:
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
TIMER2/3 MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Timer2 is a ‘Type B’ timer and Timer3 is a
‘Type C’ timer. Please refer to appropriate
timer type in
Characteristics”.
depicts the simplified block diagram of the
Figure 10-2
Section 23.0 “Electrical
and
Figure 10-3
For 32-bit timer/counter operation, Timer2 is the lsw
and Timer3 is the msw of the 32-bit timer.
16-Bit Mode: In the 16-bit mode, Timer2 and Timer3
can be configured as two independent 16-bit timers.
Each timer can be set up in either 16-bit Timer mode or
16-bit Synchronous Counter mode. See
“Timer1 Module”
modes.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high-frequency
external clock inputs.
32-Bit Timer Mode: In the 32-Bit Timer mode, the
timer increments on every instruction cycle up to a
match value, preloads into the combined 32-bit Period
register, PR3/PR2, then resets to ‘0’ and continues to
count.
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the lsw (TMR2 register) will cause the
msw to be read and latched into a 16-bit holding
register, termed TMR3HLD.
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).
32-Bit Synchronous Counter Mode: In the 32-Bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit Period register, PR3/PR2, then resets
to ‘0’ and continues.
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.
Note:
dsPIC30F3010/3011
For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer3 Interrupt Flag
(T3IF) and the interrupt is enabled with the
Timer3 Interrupt Enable bit (T3IE).
for details on these two operating
DS70141F-page 71
Section 9.0
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