DSPIC30F2023T-30I/PT Microchip Technology, DSPIC30F2023T-30I/PT Datasheet - Page 187
DSPIC30F2023T-30I/PT
Manufacturer Part Number
DSPIC30F2023T-30I/PT
Description
12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023T-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2023T-30I/PTTR
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 187 of 286
- Download datasheet (5Mb)
EXAMPLE 16-1:
16.15 Changing A/D Clock
In general, the ADC cannot accept changes to the ADC
clock divisor while ADON = 1. If the user makes A/D
clock changes while ADON = 1, the results will be
indeterminate.
16.16 Sample and Conversion
The ADC module always assigns two ADC clock peri-
ods for the sampling process. When operating at the
maximum conversion rate of 2 Msps per channel, the
sampling period is:
© 2006 Microchip Technology Inc.
; The actual pair conversion interrupt handler
; Don't forget to pop the stack when done and return from interrupt
ADC_PAIR0_PROC:
ADC_PAIR1_PROC:
ADC_PAIR2_PROC:
ADC_PAIR3_PROC:
ADC_PAIR4_PROC:
ADC_PAIR5_PROC:
2 x 41.6 nsec = 83.3 nsec.
...
POP.S
RETFIE
...
POP.S
RETFIE
...
POP.S
RETFIE
...
POP.S
RETFIE
...
POP.S
RETFIE
...
POP.S
RETFIE
ADC BASE REGISTER CODE (CONTINUED)
; The ADC pair 0 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
; The ADC pair 1 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
; The ADC pair 2 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
; The ADC pair 3 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
; The ADC pair 4 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
; The ADC pair 5 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
Preliminary
Each ADC pair specified in the ADCPCx registers ini-
tiates a sample operation when the selected trigger
event occurs. The conversion of the sampled analog
data occurs as resources become available.
If a new trigger event occurs for a specific channel
before a previous sample and convert request for that
channel has been processed, the newer request is
ignored. It is the user’s responsibility not to exceed the
conversion rate capability for the module.
The actual conversion process requires 10 additional
ADC clocks. The conversion is processed serially, bit 9
first, then bit 8, down to bit 0. The result is stored when
the conversion is completed.
dsPIC30F1010/202X
DS70178C-page 185
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