DSPIC30F1010-30I/MM Microchip Technology, DSPIC30F1010-30I/MM Datasheet - Page 188
DSPIC30F1010-30I/MM
Manufacturer Part Number
DSPIC30F1010-30I/MM
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010-30I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F1010-30I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 188 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
16.17 A/D Sample and Convert Timing
The sample and hold circuits assigned to the input pins
have their own timing logic that is triggered when an
external sample and convert request (from PWM or
TMR) is made. The sample and hold circuits have a
fixed two clock data sample period. When the sample
has been acquired, then the ADC control logic is noti-
FIGURE 16-3:
DS70178C-page 186
adc_clk
sample_even
sample_odd
connect_first
connect_second
convert_en
capture_first_data
capture_second_data
state counter
0
1
10th 9th 8th
2
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 0, NOT BUSY
3
4
T
7th
AD
5
6th
6
5th
7
4th
8
3rd 2nd 1st
9
Preliminary
10
11
10th 9th 8th
fied of a pending request, then the conversion is
performed as the conversion resources become
available.
The ADC module always converts pairs of analog input
channels, so a typical conversion process requires 24
clock cycles.
12
13
14
15
7th
16
6th
17
5th
© 2006 Microchip Technology Inc.
18
4th
19
3rd
20
2nd 1st
21
0
1
2
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