CS4362-KQ Cirrus Logic Inc, CS4362-KQ Datasheet - Page 29

• Manufacturer Part Number: CS4362-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4362-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The CS4362 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).
6.1
On the CS4362 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a I
control port is enabled, these pins are dedicated to
control port functionality.
To prevent audible artifacts the CPEN bit (see Sec-
tion 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how-
ever, setting this bit after the Stand-Alone power-
up sequence has completed can cause audible arti-
facts.
6.2
The control port has 2 formats: SPI and I
the CS4362 operating as a slave device.
If I
to VLC or GND. If the CS4362 ever detects a high
DS257F1
2
C operation is desired, AD0/CS should be tied
Enabling the Control Port
Format Selection
2
C or SPI write. Once the
2
C, with
to low transition on AD0/CS after power-up and af-
ter the control port is activated , SPI format will be
selected.
6.3
In I
Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an ac-
knowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VLC or GND as re-
quired. The upper 6 bits of the 7 bit address field
must be 001100.
Note: MCLK is required during all I
tions. Please see reference 4 for further details.
6.3.1
To communicate with the CS4362, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-
lowed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS4362 to acknowledge between
each byte. To end the transaction, send a STOP
condition.
6.3.2
To communicate with the CS4362, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi-
tion.
2
C Format, SDA is a bidirectional data line.
I
2
Writing in I
Reading in I
C Format
2
C Format
2
C Format
CS4362
2
C transac-
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