CS4362-KQ Cirrus Logic Inc, CS4362-KQ Datasheet - Page 28

• Manufacturer Part Number: CS4362-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4362-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.6
The CS4362 has two serial clock and two left/right
clock inputs. The SDINxCLK bits in the control
port allow the user to set which SCLK/LRCK pair
is used to latch the data for each SDINx pin. The
clocks applied to LRCK1 and LRCK2 must be de-
rived from the same MCLK and must be exact fre-
quency multiples of each other as specified in the
“Switching Characteristics” table on page 8. When
using both SCLK1/LRCK1 and SCLK2/LRCK2, if
either SCLK/LRCK pair loses synchronization
then both SCLK/LRCK pairs will go through a re-
time period where the device is re-evaluating clock
ratios. During the retime period all DAC pairs are
temporarily inactive, outputs are muted, and the
mute control pins will go active according to the
MUTEC bits.
If unused, SCLK2 and LRCK2 should be tied static
low and SDINx bits should all be set to
SCLK1/LRCK1.
In stand-alone mode all DAC pairs use SCLK1 and
LRCK1 for timing and SCLK2/LRCK2 should be
tied to ground.
5.7
In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK1) high and applying the
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.
In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected
28
Clock Source Selection
Using DSD mode
DSD rate and MCLK ratio. To access the full range
of DSD clocking modes (other than 64x DSD 4x
MCLK and 128x DSD 2x MCLK) the following
additional register sequence needs to be written:
99h to register 00h
80h to register 1Ah
00h to register 00h
When exiting DSD mode the following additional
sequence needs to be written:
99h to register 00h
00h to register 1Ah
00h to register 00h
During DSD operation, the PCM related pins
should either be tied low or remain active with
clocks (except LRCK1 in Stand-Alone mode).
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).
5.8
For systems where the absolute minimum in clicks
and pops is required, it is recommended that the
MUTE bits are set prior to changing significant
DAC functions (such as changing sample rates or
clock sources). The mute bits may then be released
after clocks have settled and the proper CS4362
modes have been set.
It is required that the CS4362 be held in reset if the
minimum high/low time specs of MCLK can not be
met during clock source changes.
Recommended Procedure for
Switching Operational Modes
CS4362
DS257F1