CA3338AMZ Intersil, CA3338AMZ Datasheet - Page 6

• Manufacturer Part Number: CA3338AMZ
• Description: IC,D/A CONVERTER,SINGLE,8-BIT,CMOS,SOP,16PIN
• Manufacturer: Intersil

Specifications of CA3338AMZ

• Rohs Compliant: YES

In bipolar operation, V
voltage (the maximum voltage rating to V
observed). V
output drivers, must be returned to a point at least as
negative as V
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
an input code of 00
equal to 255/256 of V
code of FF HEX (full scale output). The difference between the
ideal and actual values of these two parameters are the
OFFSET and GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
ideal step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1
LSB, the device is monotonic. (The output will always increase
for increasing code or decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs. See Figure 4.
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.
255/256
254/256
253/256
3/256
2/256
1/256
FIGURE 3. D/A OFFSET AND GAIN ERROR
0
00
EE
REF
(SHOWN +)
INPUT CODE IN HEXADECIMAL (COMP = LOW)
OFFSET
ERROR
, which supplies the gate potential for the
01
-. Note that the maximum clocking speed
HEX
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
REF
REF
02
(zero scale output), and an output
+ (referred to V
- would be returned to a negative
03
6
REF
DD
FD
GAIN ERROR
-) with an input
must be
(SHOWN -)
FE
REF
CA3338, CA3338A
FF
- with
Dynamic Characteristics
Keeping the full-scale range (V
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
delays. The V
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7F
measured by displaying the output as the input code
alternates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each
scale transition (1F
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160Ω in parallel with the load
resistance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
0
00
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
A
HEX
ERROR
REF
to 80
C
+ (and V
HEX
HEX
A = IDEAL STEP SIZE (1/255 OF FULL
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
to 20
B
INPUT CODE
REF
SCALE -“0” SCALE VOLTAGE)
for an 8 bit device), and can be
STRAIGHT LINE
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
HEX
- if bipolar) terminal should be
REF
, 3F
+ - V
INTEGRAL LINEARITY
HEX
ERROR (SHOWN -)
REF
to 40
-) as high as
HEX
, etc.)
1
/
8