CA3338AMZ Intersil, CA3338AMZ Datasheet - Page 5

• Manufacturer Part Number: CA3338AMZ
• Description: IC,D/A CONVERTER,SINGLE,8-BIT,CMOS,SOP,16PIN
• Manufacturer: Intersil

Specifications of CA3338AMZ

• Rohs Compliant: YES

Pin Descriptions
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
and V
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
and V
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
INPUT DATA
ENABLE
PIN
LATCH
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
EE
EE
t
SU1
FIGURE 1. DATA TO LATCH ENABLE TIMING
. V
supplies.
LATCHED
V
V
DD
COMP
NAME
V
EE
V
V
REF
V
REF
D7
D6
D5
D4
D3
D2
D1
D
OUT
LE
SS
EE
DD
0
and V
optionally at ground or at a negative voltage,
+
-
Most Significant Bit
Digital Ground
Least Significant Bit. Input Data Bit
Analog Ground
Reference Voltage Negative Input
Analog Output
Reference Voltage Positive Input
Data Complement Control input. Active High
Latch Enable Input. Active Low
Digital Power Supply, +5V
SS
, are shifted to operate between V
FEEDTHROUGH
DATA
t
5
W
0
DESCRIPTION
) through D7 (weighted 2
t
Input
Data
Bits
(High = True)
H
LATCHED
t
SU2
CA3338, CA3338A
DD
DD
7
),
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
gives the delay from the input changing to the output
changing (10%), while t
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given t
and the t
the output changing, t
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
In unipolar operation, V
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from V
specifications), so V
to ground.
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
INPUT
DATA
VOLTAGE
ENABLE
OUTPUT
LATCH
H
hold time from the LE rising edge. The delay to
REF
W
REF
+ to V
SU1
REF
D1
pulse width for successful latch
REF
SU2
t
- should have a low impedance path
D2
, is now referred to the LE falling
90%
+, the (+) full-scale reference.
set up time to the LE falling edge,
t
REF
D1
- would typically be returned to
and t
- (see V
H
10%
t
r
give the set up and hold
t
S
REF
REF
- this is the (-) full-
+ input current in
1
/
2
1
LSB
/
2
LSB
D2