SAK-C164CI-8E25M Infineon Technologies, SAK-C164CI-8E25M Datasheet - Page 13

• Manufacturer Part Number: SAK-C164CI-8E25M
• Description: IC, 16BIT MCU, 64K OTP, MQFP80, 164
• Manufacturer: Infineon Technologies

Specifications of SAK-C164CI-8E25M

• Core Size: 16bit
• No. Of I/o's: 59
• Program Memory Size: 64KB
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• Oscillator Type: External Only
• No. Of Timers: 5
• Digital Ic Case Style: MQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: C164CI
• Peripherals: ADC
• Rohs Compliant: Yes

C164CI
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C164CI instruction set which includes the following
instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Semiconductor Group
13
1998-02