SAK-C164CI-8E25M Infineon Technologies, SAK-C164CI-8E25M Datasheet - Page 11

• Manufacturer Part Number: SAK-C164CI-8E25M
• Description: IC, 16BIT MCU, 64K OTP, MQFP80, 164
• Manufacturer: Infineon Technologies

Specifications of SAK-C164CI-8E25M

• Core Size: 16bit
• No. Of I/o's: 59
• Program Memory Size: 64KB
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• Oscillator Type: External Only
• No. Of Timers: 5
• Digital Ic Case Style: MQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: C164CI
• Peripherals: ADC
• Rohs Compliant: Yes

Memory Organization
The memory space of the C164CI is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bitaddressable.
The C164CI incorporates 64 KByte of on-chip ROM or OTP memory for code or constant data. The
OTP memory can be programmed by the CPU itself (in system, eg. during booting) or directly via an
external interface (eg. before assembly). The programming time is approx. 100 sec per word. An
external programming voltage V
2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register banks and even for code. A register bank can consist of up
to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose
Registers (GPRs).
1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C16x family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of two different external memory access modes, which are as follows:
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
For applications which require less than 4 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.
Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be
Semiconductor Group
limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface
pins.
PP
= 11.5 V must be supplied for this purpose (via pin EA).
11
C164CI
1998-02