P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 41

• Manufacturer Part Number: P89LPC912FDH
• Description: MCU 8BIT 80C51 1K FLASH, TSSOP14
• Manufacturer: NXP Semiconductors

Specifications of P89LPC912FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of: RoHS Compliant

NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.18.10 The 9
8.18.7 Break detect
8.18.8 Double buffering
8.18.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
8.19 Serial Peripheral Interface (SPI)
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device.
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated
when the double buffer is ready to receive new data.
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TX interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
P89LPC912/913/914 provides another high-speed serial communication interface—the
SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
Rev. 05 — 28 September 2007
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
© NXP B.V. 2007. All rights reserved.
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