LFXP2-17E-5QN208C8W LATTICE SEMICONDUCTOR, LFXP2-17E-5QN208C8W Datasheet - Page 5

• Manufacturer Part Number: LFXP2-17E-5QN208C8W
• Description: FPGA, 17K LUTS, 146 IO, DSP, 208PQFP
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXP2r

Specifications of LFXP2-17E-5QN208C8W

• No. Of Macrocells: 8500
• Family Type: LatticeXP2
• No. Of Speed Grades: 5
• No. Of I/o's: 146
• Clock Management: PLL
• Core Supply Voltage Range: 1.14V To 1.26V
• I/o Supply: RoHS Compliant

Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level)
PFU Blocks
The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro-
grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro-
grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data
sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.
All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated
with each PFU block.
Programmable
Function Units
(PFUs)
sysMEM Block
RAM
DSP Blocks
SPI Port
On-chip
Oscillator
sysCLOCK PLLs
2-2
Flexible Routing
sysIO Buffers,
Pre-Engineered Source
Synchronous Support
LatticeXP2 Family Data Sheet
Architecture
JTAG Port
Flash