MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 111

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

In the timing equations, some timing parameters are used. These parameters depend on the
implementation of the i.MX53xD PATA interface on silicon, the bus buffer used, the cable delay and
cable skew.
Freescale Semiconductor
1
Values provided where applicable.
tcable1
tcable2
tskew1
tskew2
tskew3
tskew4
tskew5
tskew6
Name
ti_dh
ti_ds
tbuf
tsui
tco
tsu
thi
T
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Propagation delay bus clock L-to-H to
Set-up time ata_data to bus clock L-to-H
Max difference in propagation delay bus clock L-to-H to any of following signals
Max difference in buffer propagation delay for any of following signals:
Max difference in buffer propagation delay for any of following signals ata_iordy,
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Max difference in cable propagation delay between (ata_dior, ata_diow,
Max difference in cable propagation delay without accounting for ground bounce
Bus clock period (AHB_CLK_ROOT)
Hold time ata_iordy edge to ata_data (UDMA-in only)
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_data (read)
Max buffer propagation delay
ata_dmack
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Table 71
shows ATA timing parameters.
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Table 71. PATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Peripheral clock frequency
(7.5 ns for 133 MHz clock)
Electrical Characteristics
Contributing Factor
Transceiver
Transceiver
Transceiver
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
Cable
Cable
Cable
Cable
Cable
15 ns
10 ns
7 ns
5 ns
4 ns
7 ns
1
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