MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 110

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
4.7.12
This section describes the timing parameters of the Parallel ATA module which are compliant with
ATA/ATAPI-6 specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA
module interface consist of a total of 29 pins. Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Table 70
modes.
The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xD PATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it
difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode
operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
110
1
SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15
SI1
SI2
SI3
ID
ATA Interface Signals
Rising edge slew rate for any signal on ATA interface
Falling edge slew rate for any signal on ATA interface
Host interface signal capacitance at the host connector
and
PATA Timing Parameters
Figure 63
i.MX53xD Applications Processors for Consumer Products, Rev. 3
define the AC characteristics of all the PATA interface signals in all data transfer
Table 70. AC Characteristics of All Interface Signals
Figure 63. PATA Interface Signals Timing Diagram
Parameter
–
40 pF where all signals have the same capacitive load value.
SI2
1
1
SI1
Symbol
C
S
S
host
rise
fall
Min
—
—
—
Freescale Semiconductor
Max
1.25
1.25
20
Unit
V/ns
V/ns
pF