LA-ISPPAC-POWR1014-01TN48E LATTICE SEMICONDUCTOR, LA-ISPPAC-POWR1014-01TN48E Datasheet - Page 31

• Manufacturer Part Number: LA-ISPPAC-POWR1014-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LA-ISPPAC-POWR1014-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• Frequency: 25MHz
• No. Of Macrocells: 24
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Software-Based Design Environment
Designers can configure the LA-ispPAC-POWR1014/A using PAC-Designer, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected
to the serial programming interface pins of the LA-ispPAC-POWR1014/A. A library of configurations is included with
basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading.
In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 25, provides access to all configurable LA-isp-
PAC-POWR1014/A elements via its graphical user interface. All analog input and output pins are represented.
Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any
element in the schematic window can be accessed via mouse operations as well as menu commands. When com-
pleted, configurations can be saved, simulated, and downloaded to devices.
Figure 25. PAC-Designer LA-ispPAC-POWR1014/A Design Entry Screen
In-System Programming
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The LA-ispPAC-POWR1014/A is an in-system programmable device. This is accomplished by integrating all E
configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compli-
ant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is
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stored on-chip, in non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all LA-
ispPAC-POWR1014/A instructions are described in the JTAG interface section of this data sheet.
Programming LA-ispPAC-POWR1014/A: Alternate Method
Some applications require that the LA-ispPAC-POWR1014/A be programmed before turning the power on to the
entire circuit board. To meet such application needs, the LA-ispPAC-POWR1014/A provides an alternate program-
ming method which enables the programming of the LA-ispPAC-POWR1014/A device through the JTAG chain with
a separate power supply applied just to the programming section of the LA-ispPAC-POWR1014/A device with the
main power supply of the board turned off.
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