LPC1227FBD64/301 NXP Semiconductors, LPC1227FBD64/301 Datasheet - Page 48
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LPC1227FBD64/301
Manufacturer Part Number
LPC1227FBD64/301
Description
MCU, 128K FLASH, CORTEX-M0, 64LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1224FBD48201.pdf
(60 pages)
Specifications of LPC1227FBD64/301
Rohs Compliant
YES
Featured Product
LPC122x Cortex-M0 Microcontrollers
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
45MHz
Connectivity
I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
55
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
LPC1200
No. Of I/o's
55
Ram Memory Size
8KB
Cpu Speed
30MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5164
LPC1227FBD64/301
LPC1227FBD64/301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1227FBD64/301
Manufacturer:
NXP
Quantity:
5 000
Company:
Part Number:
LPC1227FBD64/301
Manufacturer:
NXP
Quantity:
5 000
Part Number:
LPC1227FBD64/301
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
LPC1227FBD64/301,1
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 16.
T
[1]
[2]
[3]
[4]
LPC122X
Objective data sheet
Symbol
T
SSP master
t
t
t
t
SSP slave
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
amb
cy(clk)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
T
T
T
= 25
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C; V
= 25 C; V
= (SSPCLKDIV (1 + SCR) CPSDVSR) / f
= 12 T
C.
Dynamic characteristics: SSP pins in SPI mode
11.5 SSP/SPI interface
cy(PCLK)
DD(3V3)
Parameter
clock cycle time
data set-up time
data hold time
data output valid time
data output hold time
data set-up time
data hold time
data output valid time
data output hold time
main
.
= 3.3 V; V
DD(3V3)
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
DD(IO)
= 3.0 V to 3.6 V; V
= 3.3 V.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
DD(IO)
main
Conditions
when only
transmitting
when only
receiving
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
. The clock cycle time derived from the SPI bit rate T
= 3.0 V to 3.6 V.
[1]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
Min
<tbd>
<tbd>
15
0
-
0
0
3 T
-
-
32-bit ARM Cortex-M0 microcontroller
cy(PCLK)
+ 4
Max
-
-
-
-
10
-
-
-
3 T
2 T
cy(PCLK)
cy(PCLK)
cy(clk)
LPC122x
© NXP B.V. 2011. All rights reserved.
is a function of the
+ 11
+ 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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