PIC24HJ256GP210A-I/PF Microchip Technology, PIC24HJ256GP210A-I/PF Datasheet - Page 219

• Manufacturer Part Number: PIC24HJ256GP210A-I/PF
• Description: IC, 16BIT MCU, PIC24H, 40MIPS, TQFP-100
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP210A-I/PF

• Controller Family/series: PIC24
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 9
• Interface: I2C, LIN, SPI, UART
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 256 KB
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Embedded Interface Type: I2C, LIN, SPI, UART
• Rohs Compliant: Yes
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.0
PIC24HJXXXGPX06A/X08A/X10A
several features intended to maximize application flex-
ibility and reliability, and minimize cost through elimina-
tion of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 21-1:
 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bits, read as ‘0’.
Address
programming capability
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
Note 1: This data sheet summarizes the features
2: When read, this bit returns the current programmed value.
3: This bit is unimplemented on PIC24HJ64GPX06A/X08A/X10A and PIC24HJ128GPX06A/X08A/X10A
4: These bits are reserved and always read as ‘1’.
2: Some registers and associated bits
SPECIAL FEATURES
devices and reads as ‘0’.
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
23.
(DS70239), Section 24. “Programming
and Diagnostics” (DS70246), and Sec-
tion
(DS70231) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Name
DEVICE CONFIGURATION REGISTER MAP
25.
“CodeGuard™
FWDTEN
“Device
IESO
Bit 7
—
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
PIC24HJXXXGPX06A/X08A/X10A
Reserved
devices
Reserved
Configuration”
WINDIS
(1)
Bit 6
—
Security”
(4)
(2)
include
PLLKEN
Preliminary
JTAGEN
Bit 5
—
—
—
—
—
(3)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
21.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 21-1.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
Bit 4
—
—
—
—
—
—
—
Configuration Bits
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
—
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
DS70592B-page 219
Bit 1
ICS<1:0>
GWRP
BWRP
SWRP
Bit 0