LPC2148FBD64 NXP Semiconductors, LPC2148FBD64 Datasheet
LPC2148FBD64
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LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC Rev. 03 — 19 October 2007 1. General description The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time ...
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... Type number LPC2141FBD64 32 kB LPC2142FBD64 64 kB LPC2144FBD64 128 kB LPC2146FBD64 256 kB LPC2148FBD64 512 kB [1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage. LPC2141_42_44_46_48_3 ...
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... NXP Semiconductors 4. Block diagram LPC2141/42/44/46/48 P0[31:28] and FAST GENERAL P0[25:0] PURPOSE I/O P1[31:16] ARM7 local bus INTERNAL SRAM CONTROLLER 8 kB/16 kB SRAM EXTERNAL EINT3 to EINT0 INTERRUPTS 4 CAP0 CAPTURE/COMPARE 4 CAP1 (W/EXTERNAL CLOCK) 8 MAT0 TIMER 0/TIMER 1 8 MAT1 AD0[7:6] and AD0[4:1] ADC0 AND ADC1 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.21/PWM5/CAP1.3 1 P0.22/CAP0.0/MAT0 RTCX1 4 P1.19/TRACEPKT3 RTCX2 DDA P1.18/TRACEPKT2 8 P0.25/AD0 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 2. LPC2141 pinning LPC2141_42_44_46_48_3 Product data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2141 Rev. 03 — 19 October 2007 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/EINT2 44 P1.21/PIPESTAT0 P0.14/EINT1/SDA1 40 P1 ...
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... NXP Semiconductors P0.21/PWM5/CAP1.3 1 P0.22/CAP0.0/MAT0 RTCX1 P1.19/TRACEPKT3 4 RTCX2 DDA P1.18/TRACEPKT2 8 P0.25/AD0.4/AOUT P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 3. LPC2142 pinning LPC2141_42_44_46_48_3 Product data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2142 Rev. 03 — 19 October 2007 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/EINT2 44 P1.21/PIPESTAT0 P0.14/EINT1/SDA1 40 P1.22/PIPESTAT1 39 P0.13/MAT1.1 38 P0.12/MAT1.0 37 P0.11/CAP1.1/SCL1 36 P1 ...
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... NXP Semiconductors P0.21/PWM5/AD1.6/CAP1 P0.22/AD1.7/CAP0.0/MAT0.0 RTCX1 3 P1.19/TRACEPKT3 4 RTCX2 DDA P1.18/TRACEPKT2 8 9 P0.25/AD0.4/AOUT P1.17/TRACEPKT1 12 13 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 14 P0.30/AD0.3/EINT3/CAP0 P1.16/TRACEPKT0 Fig 4. LPC2144/2146/2148 pinning LPC2141_42_44_46_48_3 Product data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2144/2146/2148 Rev. 03 — 19 October 2007 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/RI1/EINT2/AD1.5 44 P1.21/PIPESTAT0 P0.14/DCD1/EINT1/SDA1 40 P1.22/PIPESTAT1 39 P0.13/DTR1/MAT1.1/AD1 ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 [1] P0.0/TXD0/ 19 PWM1 [2] P0.1/RXD0/ 21 PWM3/EINT0 [3] P0.2/SCL0/ 22 CAP0.0 [3] P0.3/SDA0/ 26 MAT0.0/EINT1 [4] P0.4/SCK0/ 27 CAP0.1/AD0.6 [4] P0.5/MISO0/ 29 MAT0.1/AD0.7 [4] P0.6/MOSI0/ 30 CAP0.2/AD1.0 [2] P0.7/SSEL0/ 31 PWM2/EINT2 [4] P0.8/TXD1/ 33 PWM4/AD1.1 LPC2141_42_44_46_48_3 Product data sheet Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [2] P0.9/RXD1/ 34 PWM6/EINT3 [4] P0.10/RTS1/ 35 CAP1.0/AD1.2 [3] P0.11/CTS1/ 37 CAP1.1/SCL1 [4] P0.12/DSR1/ 38 MAT1.0/AD1.3 [4] P0.13/DTR1/ 39 MAT1.1/AD1.4 [3] P0.14/DCD1/ 41 EINT1/SDA1 [4] P0.15/RI1/ 45 EINT2/AD1.5 [2] P0.16/EINT0/ 46 MAT0.2/CAP0.2 [1] P0.17/CAP1.2/ 47 SCK1/MAT1.2 LPC2141_42_44_46_48_3 Product data sheet Type Description I/O P0.9 — General purpose input/output digital pin (GPIO) I RXD1 — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P0.18/CAP1.3/ 53 MISO1/MAT1.3 [1] P0.19/MAT1.2/ 54 MOSI1/CAP1.2 [2] P0.20/MAT1.3/ 55 SSEL1/EINT3 [4] P0.21/PWM5/ 1 AD1.6/CAP1.3 [4] P0.22/AD1.7/ 2 CAP0.0/MAT0.0 [1] P0.23/V 58 BUS [5] P0.25/AD0.4/ 9 AOUT [4] P0.28/AD0.1/ 13 CAP0.2/MAT0.2 [4] P0.29/AD0.2/ 14 CAP0.3/MAT0.3 [4] P0.30/AD0.3/ 15 EINT3/CAP0.0 LPC2141_42_44_46_48_3 Product data sheet Type Description I/O P0.18 — General purpose input/output digital pin (GPIO) I CAP1.3 — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [6] P0.31/UP_LED/ 17 CONNECT P1.0 to P1.31 [6] P1.16/ 16 TRACEPKT0 [6] P1.17/ 12 TRACEPKT1 [6] P1.18/ 8 TRACEPKT2 [6] P1.19/ 4 TRACEPKT3 [6] P1.20/ 48 TRACESYNC [6] P1.21/ 44 PIPESTAT0 [6] P1.22/ 40 PIPESTAT1 [6] P1.23/ 36 PIPESTAT2 [6] P1.24/ 32 TRACECLK [6] P1.25/EXTIN0 28 [6] P1.26/RTCK 24 [6] P1.27/TDO 64 LPC2141_42_44_46_48_3 Product data sheet Type Description O P0.31 — ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [6] P1.28/TDI 60 [6] P1.29/TCK 56 [6] P1.30/TMS 52 [6] P1.31/TRST [8] RESET 57 [9] XTAL1 62 [9] XTAL2 61 [9] RTCX1 3 [9] RTCX2 18, 25, 42 SSA V 23, 43 DDA VREF 63 VBAT 49 [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC) ...
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... NXP Semiconductors 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB and static RAM respectively. In case of LPC2146/48 only SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution ...
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... NXP Semiconductors 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors 6.7 Fast general purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow the setting or clearing of any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins ...
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... NXP Semiconductors 6.9 10-bit DAC The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. 6.9.1 Features • 10-bit DAC • Buffered output • Power-down mode available • Selectable speed versus power 6.10 USB 2.0 device controller The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals ...
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... NXP Semiconductors 6.11 UARTs The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
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... NXP Semiconductors • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer • The I 6.13 SPI serial I/O controller The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
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... NXP Semiconductors 6.15.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler • External event counter or timer operation • Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions, a capture event may also optionally generate an interrupt • ...
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... NXP Semiconductors • Ultra-low power design to support battery powered systems • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year • Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1, programmable reference clock divider allows fi ...
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... NXP Semiconductors • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • ...
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... NXP Semiconductors When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions ...
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... NXP Semiconductors Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode. 6.19.7 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip fl ...
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... NXP Semiconductors 6.20 Emulation and debugging The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF i(VREF) V analog input voltage IA V input voltage ...
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... NXP Semiconductors 8. Static characteristics Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. a Symbol Parameter V supply voltage DD V analog 3.3 V pad supply DDA voltage V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF i(VREF) Standard port pins, RESET, RTCK ...
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... NXP Semiconductors Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. a Symbol Parameter I active mode supply DD(act) current I Power-down mode supply DD(pd) current I Power-down mode battery BATpd supply current I active mode battery BATact supply current I optimized active mode BATact(opt) ...
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... NXP Semiconductors Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. a Symbol Parameter V input voltage on pin i(RTCX1) RTCX1 V output voltage on pin o(RTCX2) RTCX2 USB pins I OFF-state output current OZ V bus supply voltage BUS V differential input sensitivity |(D differential common mode ...
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... NXP Semiconductors Table 6. ADC static characteristics +85 C unless otherwise specified. ADC frequency 4.5 MHz. DDA a Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics LPC2141_42_44_46_48_3 Product data sheet ...
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... NXP Semiconductors ADx.y Fig 7. Suggested ADC interface - LPC2141/42/44/46/48 ADx.y pin LPC2141_42_44_46_48_3 Product data sheet LPC2141/42/44/46/ SAMPLE Rev. 03 — 19 October 2007 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers R vsi ADx.y V EXT 002aab834 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 9. Dynamic characteristics Table 7. Dynamic characteristics of USB pins (full-speed pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 9.1 Timing V 0 0.2V 0. Fig 8. External clock timing t PERIOD differential data lines Fig 9. Differential data-to-EOP transition skew and EOP width 10. Application information 10.1 Suggested USB interface solutions LPC2141/42/ 44/46/48 Fig 10. LPC2141/42/44/46/48 USB interface using the CONNECT function on pin 17 ...
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... NXP Semiconductors LPC2141/42/ 44/46/48 Fig 11. LPC2141/42/44/46/48 USB interface using the UP_LED function on pin 17 LPC2141_42_44_46_48_3 Product data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 1.5 k UP_LED VBUS Rev. 03 — 19 October 2007 USB-B connector 002aab562 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 11. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 12. Abbreviations Table 9. Acronym ADC BOD CPU DAC DCC DMA EOP FIFO GPIO PLL POR PWM RAM SE0 SPI SRAM SSP UART USB VPB LPC2141_42_44_46_48_3 Product data sheet Acronym list Description Analog-to-Digital Converter Brown-Out Detection Central Processing Unit Digital-to-Analog Converter ...
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... Data sheet status Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. Product data sheet Preliminary data sheet Rev. 03 — ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Functional description . . . . . . . . . . . . . . . . . . 12 6.1 Architectural overview 6.2 On-chip flash program memory . . . . . . . . . . . 12 6.3 On-chip static RAM ...