PIC16LF1827-I/MV Microchip Technology, PIC16LF1827-I/MV Datasheet - Page 258

• Manufacturer Part Number: PIC16LF1827-I/MV
• Description: IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-I/MV

• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4kWords
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-UFQFN Exposed Pad
• Processor Series: PIC16LF
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1826/27
24.5.4
This section describes a standard sequence of events
for the MSSPx module configured as an I
10-bit Addressing mode.
Figure 24-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
14. If SEN bit of SSPxCON2 is set, CKP is cleared
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41391C-page 258
Note: Updates to the SSPxADD register are not
Note: If the low address does not match, SSPxIF
Bus starts Idle.
Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
Slave sends ACK and SSPxIF is set.
Software clears the SSPxIF bit.
Software
SSPxBUF clearing the BF flag.
Slave loads low address into SSPxADD,
releasing SCLx.
Master sends matching low address byte to the
Slave; UA bit is set.
Slave sends ACK and SSPxIF is set.
from SSPxBUF clearing BF.
clocks out the slaves ACK on the 9th SCLx
pulse; SSPxIF is set.
by hardware and the clock is stretched.
clearing BF.
SCLx.
SLAVE MODE 10-BIT ADDRESS
RECEPTION
allowed until after the ACK sequence.
and UA are still set so that the slave software
can set SSPxADD back to the high address.
BF is not set because there is no match.
CKP is unaffected.
reads
received
2
C communication.
address
2
C Slave in
from
Preliminary
24.5.5
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCLx line is held low are the
same. Figure 24-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 24-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
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