LPC2103FBD48-S NXP Semiconductors, LPC2103FBD48-S Datasheet - Page 8

• Manufacturer Part Number: LPC2103FBD48-S
• Description: IC, 32BIT MCU, ARM7, 75MHZ, LQFP-48
• Manufacturer: NXP Semiconductors

Specifications of LPC2103FBD48-S

• Controller Family/series: (ARM7)
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 70MHz
• No. Of Timers: 6
• Digital Ic Case Style: LQFP
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 3.
LPC2101_02_03_4
Product data sheet
Symbol
P0.22/AD0.0
P0.23/AD0.1
P0.24/AD0.2
P0.25/AD0.6
P0.26/AD0.7
P0.27/TRST/
CAP2.0
P0.28/TMS/
CAP2.1
P0.29/TCK/
CAP2.2
P0.30/TDI/
MAT3.3
P0.31/TDO
RTCX1
RTCX2
RTCK
XTAL1
XTAL2
DBGSEL
RST
Pin description
Pin
32
33
34
38
39
8
9
10
15
16
20
25
26
11
12
27
6
[1]
[1]
[3]
[3]
[3]
[3]
[3]
[1]
[1]
[1]
[7][8]
[7][8]
[7]
…continued
Type
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
O
O
O
I
O
I/O
I
O
I
I
Description
P0.22 — General purpose input/output digital pin.
AD0.0 — ADC 0, input 0.
P0.23 — General purpose input/output digital pin.
AD0.1 — ADC 0, input 1.
P0.24 — General purpose input/output digital pin.
AD0.2 — ADC 0, input 2.
P0.25 — General purpose input/output digital pin.
AD0.6 — ADC 0, input 6.
P0.26 — General purpose input/output digital pin.
AD0.7 — ADC 0, input 7.
P0.27 — General purpose input/output digital pin.
TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.0 — Capture input for Timer 2, channel 0.
P0.28 — General purpose input/output digital pin.
TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
CAP2.1 — Capture input for Timer 2, channel 1.
P0.29 — General purpose input/output digital pin.
TCK — Test Clock for JTAG interface. This clock must be slower than
CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this
pin is automatically configured for use with EmbeddedICE (Debug mode).
CAP2.2 — Capture input for Timer 2, channel 2.
P0.30 — General purpose input/output digital pin.
TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
MAT3.3 — PWM output 3 for Timer 3.
P0.31 — General purpose output only digital pin.
TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is
automatically configured for use with EmbeddedICE (Debug mode).
Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V.
Output from the RTC oscillator circuit.
Returned test clock output: Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.
Input to the oscillator circuit and internal clock generator circuits. Input voltage
must not exceed 1.8 V.
Output from the oscillator amplifier.
Debug select: When LOW, the part operates normally. When externally
pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the
part is in Debug mode
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
Rev. 04 — 2 June 2009
[9]
. Input with internal pull-down.
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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