LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 17

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LPC1764FBD100

Manufacturer Part Number
LPC1764FBD100
Description
IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
Manufacturer
NXP Semiconductors
Datasheets

Specifications of LPC1764FBD100

Controller Family/series
(ARM Cortex)
No. Of I/o's
70
Ram Memory Size
32KB
Cpu Speed
100MHz
No. Of Timers
4
Interface
CAN, I2C, SPI, UART
Core Size
32 Bit
Program Memory Size
128KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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NXP Semiconductors
[4]
[5]
[6]
[7]
[8]
[9]
[10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC.
[11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
[12] When the RTC is not used, connect VBAT to V
LPC1769_68_67_66_65_64_63
Product data sheet
Open-drain 5 V tolerant digital I/O pad, compatible with I
output functionality. When power is switched off, this pin connected to the I
Open-drain configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only). This pad is not 5 V tolerant.
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled.
5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
All information provided in this document is subject to legal disclaimers.
DD(REG)(3V3)
Rev. 8 — 14 November 2011
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
and leave RTCX1 floating.
LPC1769/68/67/66/65/64/63
2
C-bus is floating and does not disturb the I
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
2
C lines.
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