IS61LV5128AL-10TLI INTEGRATED SILICON SOLUTION (ISSI), IS61LV5128AL-10TLI Datasheet - Page 7

• Manufacturer Part Number: IS61LV5128AL-10TLI
• Description: IC, SRAM, 4MBIT, 10NS, TSOP-2-44
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS61LV5128AL-10TLI

• Memory Size: 4Mbit
• Memory Configuration: 512K X 8
• Access Time: 10ns
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TSOP-2
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LV5128AL
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to
AC WAVEFORMS
WRITE CYCLE NO. 1
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
04/15/05
Symbol
levels of 0V to 3.0V and output loading specified in Figure 1.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
t
t
t
t
t
t
t
t
t
t
t
WC
SCE
AW
HA
PWE
PWE
SD
HD
HZWE
LZWE
SA
1
2
ADDRESS
(2)
(2)
D
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
OUT
WE
D
CE
IN
(1,2)
DATA UNDEFINED
t
(CE Controlled, OE = HIGH or LOW)
SA
t
HZWE
t
VALID ADDRESS
AW
t
t
1-800-379-4774
PWE1
PWE2
t
t
Min. Max.
SCE
WC
10
10
—
8
8
0
0
8
6
0
2
-10
(1,3)
HIGH-Z
—
—
—
—
—
—
—
—
—
—
(Over Operating Range)
5
t
SD
DATA
Min. Max.
12
12
—
8
8
0
0
8
6
0
2
-12
IN
VALID
—
—
—
—
—
—
—
—
—
—
6
t
HD
t
LZWE
t
HA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE_WR1.eps
ISSI
®
7