S29AL032D70BFI030 Spansion Inc., S29AL032D70BFI030 Datasheet - Page 14

• Manufacturer Part Number: S29AL032D70BFI030
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL032D70BFI030

• Memory Size: 32Mbit
• Memory Configuration: 4M X 8 / 2M X 16
• Ic Interface Type: CFI, Parallel
• Access Time: 70ns
• Memory Case Style: FBGA
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
7. Device Bus Operations
Legend
L = Logic Low = V
Notes
1. When the ACC pin is at V
2. Addresses are A20:A0 in word mode (BYTE# = V
3. The sector protect and sector unprotect functions may also be implemented via programming equipment.
4. If WP#/ACC = V
5. D
6. Models 03, 04 only
7.1
12
Read
Write
Accelerated Program
(Note 6)
Standby
Output Disable
Reset
Sector Protect
Sector Unprotect
(Note 3)
Temporary Sector
Unprotect
last protected or unprotected. If WP#/ACC = V
IN
or D
(Note 1)
Operation
OUT
Valid Combinations
Word/Byte Configuration (Models 03, 04 Only)
as required by command sequence, data polling, or sector protection algorithm.
(Note 3)
IL
, H = Logic High = V
IL
, the two outermost boot sectors remain protected. If WP#/ACC = V
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device.
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
HH
V
, the device enters the accelerated program mode. See
0.3 V
CE#
CC
X
X
L
L
L
L
L
L
±
IH
OE#
, V
H
H
H
H
H
X
X
X
L
ID
= 12.0 ± 0.5 V, X = Don’t Care, A
WE#
HH
H
X
H
X
X
L
L
L
L
Table 7.1 S29AL032D Device Bus Operations
, all sectors are unprotected.
IH
), A20:A-1 in byte mode (BYTE# = V
RESET#
V
0.3 V
V
V
V
CC
H
H
H
H
L
ID
ID
ID
±
WP#(Note
S29AL032D
(Note 4)
(Note 4)
(Note 4)
IN
V
L/H
L/H
L/H
L/H
D a t a
H
HH
= Address In, D
6)/ACC
IH
, the two outermost boot sector protection depends on whether they were
IL
).
S h e e t
A1 = H, A0 = L
A1 = H, A0 = L
IN
SA, A6 = H,
Addresses
SA, A6 = L,
= Data In, D
(Note 3)
Table 7.1
A
A
A
A
X
X
X
IN
IN
IN
IN
OUT
lists the device bus operations, the
= Data Out
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
S29AL032D_00_A9 January 19, 2007
(Note 5)
(Note 5)
(Note 5)
BYTE#
High-Z
High-Z
High-Z
= V
D
OUT
X
X
DQ8–DQ15
IH
High-Z, DQ15 =
DQ8–DQ14 =
BYTE# = V
High-Z
High-Z
High-Z
High-Z
(Note 6)
A-1
X
X
IL