A25L016M-F AMIC, A25L016M-F Datasheet - Page 23

IC, SM, FLASH, 16MB, SPI, TOP BOOT

A25L016M-F

Manufacturer Part Number
A25L016M-F
Description
IC, SM, FLASH, 16MB, SPI, TOP BOOT
Manufacturer
AMIC
Datasheet

Specifications of A25L016M-F

Memory Size
16Mbit
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOP
No. Of Pins
8
Base Number
25L016
Frequency
100MHz
Interface
Serial, SPI
Package / Case
SOP
Memory Type
Uniform Sector Flash
Memory Configuration
2M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A25L016M-F
Manufacturer:
MOT
Quantity:
3 290
Part Number:
A25L016M-F
Manufacturer:
AMIC
Quantity:
20 000
Company:
Part Number:
A25L016M-F
Quantity:
555
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip
Select (
Data Input (DIO). Chip Select (
entire duration of the sequence.
The instruction sequence is shown in Figure 15. Chip Select
(
code has been latched in, otherwise the Block Erase
Figure 15. Chip Erase (CE) Instruction Sequence
(October, 2010, Version 1.4)
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial
DIO
C
S
Note:. Address bits A23 to A21 are Don’t Care, for A25L016
S
) must be driven Low for the
0
1 2 3
Instruction
22
4 5 6 7
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Chip Erase cycle (whose duration
is t
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block
Protect (TB, BP2, BP1, BP0) bits are 0. The Chip Erase (CE)
instruction is ignored if one, or more, blocks are protected.
CE
) is initiated. While the Chip Erase cycle is in progress,
.
AMIC Technology Corp.
A25L016 Series
S
) is

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