25LC1024-I/SN Microchip Technology, 25LC1024-I/SN Datasheet - Page 14

• Manufacturer Part Number: 25LC1024-I/SN
• Description: IC, EEPROM, 1MBIT, SERIAL, 20MHZ, SOIC-8
• Manufacturer: Microchip Technology

Specifications of 25LC1024-I/SN

• Memory Size: 1Mbit
• Ic Interface Type: SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Memory Configuration: 128K X 8
• Interface Type: Serial, SPI

25AA1024/25LC1024
2.10
The Sector Erase function will erase all bits (FFh)
inside the given sector. A Write Enable (WREN) instruc-
tion must be given prior to attempting a Sector Erase.
This is done by setting CS low and then clocking out
the proper instruction into the 25XX1024. After all
eight bits of the instruction are transmitted, the CS
must be brought high to set the write enable latch.
The Sector Erase function is entered by driving CS
low, followed by the instruction code Figure 2-9, and
three address bytes. Any address inside the sector to
be erased is a valid address.
FIGURE 2-9:
DS21836A-page 14
SECTOR ERASE
SCK
SO
CS
SI
SECTOR ERASE SEQUENCE
1
0
1
1
0
instruction
2
1
3
1
4
0
5
high-impedance
Preliminary
0
6
0
7
23 22 21 20
8
CS must then be driven high after the last bit if the
address or the Sector Erase will not execute. Once the
CS is driven high the self-timed Sector Erase cycle is
started. The WIP bit in the Status Register can be read
to determine when the Sector Erase cycle is complete.
If a Sector Erase instruction is given to an address that
has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
See Table 2-3 for Sector Addressing.
9 10 11
24-bit address
29 30 31
2
 2003 Microchip Technology Inc.
1
0