GAL16V8D-25QPN LATTICE SEMICONDUCTOR, GAL16V8D-25QPN Datasheet - Page 3

• Manufacturer Part Number: GAL16V8D-25QPN
• Description: IC, GAL, 25NS, DIP-20
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of GAL16V8D-25QPN

• Logic Type: EEPLD
• Propagation Delay: 25ns
• No. Of I/o's: 8
• Frequency: 41.6MHz
• Supply Current Max: 55mA
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Logic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ-
ual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
Output Logic Macrocell (OLMC)
Compiler Support for OLMC
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
"Registered"
GAL16V8_R
Registered
G16V8MS
P16V8R
P16V8R
G16V8R
2
1
GAL16V8_C7
"Complex"
G16V8MA
Complex
P16V8C
G16V8C
P16V8C
2
3
1
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Emulated by GAL16V8
PAL Architectures
GAL16V8_C8
G16V8AS
G16V8AS
P16V8AS
"Simple"
Specifications GAL16V8
16RP8
16RP6
16RP4
P16V8C
16R8
16R6
16R4
16H8
16P8
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
16L8
10L8
12L6
14L4
16L2
Simple
2
1
3
Auto Mode Select
Global OLMC Mode
GAL16V8A
GAL16V8
P16V8A
Registered
Registered
Registered
Registered
Registered
Registered
G16V8
G16V8
P16V8
GAL16V8
Complex
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple