EPF8282ALC84-4N Altera, EPF8282ALC84-4N Datasheet - Page 24
![IC, PLD, 208 MACROCELL, 60MHZ, PLCC-84](/photos/19/4/190431/4243405_sml.jpg)
EPF8282ALC84-4N
Manufacturer Part Number
EPF8282ALC84-4N
Description
IC, PLD, 208 MACROCELL, 60MHZ, PLCC-84
Manufacturer
Altera
Series
FLEX 8Kr
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8282ALC84-4N
No. Of Macrocells
208
No. Of I/o's
64
Global Clock Setup Time
1.2ns
Frequency
60MHz
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
Family Name
FLEX 8000
Number Of Usable Gates
2500
Number Of Logic Blocks/elements
208
# Registers
282
# I/os (max)
78
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
208
Device System Gates
2500
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ALTERA
Quantity:
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FLEX 8000 Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
24
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during
EXTEST
BYPASS
Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions
JTAG Instruction
normal device operation, and permits an initial data pattern to be output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation.
MultiVolt I/O Interface
The FLEX 8000 device architecture supports the MultiVolt I/O interface
feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A
devices to interface with systems with differing supply voltages. These
devices in all packages—except for EPF8636A devices in 84-pin PLCC
packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of V
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply. With
a 5.0-V V
compatible with 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with V
incur a nominally greater timing delay of t
on page
The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A
devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG
circuitry support the JTAG instructions shown in
26.
CCINT
level, input voltages are at TTL levels and are therefore
CC
pins for internal operation and input buffers
Description
OD2
CCIO
instead of t
levels lower than 4.75 V
Table
Altera Corporation
6.
OD1
. See
Table 8