EPF8282ALC84-4N Altera, EPF8282ALC84-4N Datasheet - Page 18

• Manufacturer Part Number: EPF8282ALC84-4N
• Description: IC, PLD, 208 MACROCELL, 60MHZ, PLCC-84
• Manufacturer: Altera
• Series: FLEX 8Kr

Specifications of EPF8282ALC84-4N

• No. Of Macrocells: 208
• No. Of I/o's: 64
• Global Clock Setup Time: 1.2ns
• Frequency: 60MHz
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Family Name: FLEX 8000
• Number Of Usable Gates: 2500
• Number Of Logic Blocks/elements: 208
• # Registers: 282
• # I/os (max): 78
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 208
• Device System Gates: 2500
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 9. FLEX 8000 Device Interconnect Resources
18
1
1
8
8
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
LAB Local
Interconnect
IOE
IOE
IOE
IOE
Column
Interconnect
LAB
LAB
A1
B1
IOE
IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate.
IOE
IOE
Cascade &
Carry Chain
Row
Interconnect
Figure 10
LAB
LAB
A2
B2
shows the IOE block diagram.
IOE
IOE
IOE
IOE
See Figure 12
for details.
IOE
IOE
IOE
IOE
Altera Corporation
1
1
8
8
See Figure 11
for details.