EPM7256AEQC208-7N Altera, EPM7256AEQC208-7N Datasheet - Page 13
![IC PLD EEPROM 256 MACROCELL 7.5NS QFP208](/photos/19/4/190423/4732026_sml.jpg)
EPM7256AEQC208-7N
Manufacturer Part Number
EPM7256AEQC208-7N
Description
IC PLD EEPROM 256 MACROCELL 7.5NS QFP208
Manufacturer
Altera
Series
MAX 7000AEr
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AEQC208-7N
Cpld Type
EEPROM
No. Of Macrocells
256
No. Of I/o's
164
Propagation Delay
7.5ns
Global Clock Setup Time
3.9ns
Frequency
172.4MHz
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7256AEQC208-7N
Manufacturer:
ALTERA
Quantity:
25
Part Number:
EPM7256AEQC208-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
13