5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 61

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5M240ZT100C5N

Manufacturer Part Number
5M240ZT100C5N
Description
IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M240ZT100C5N

Cpld Type
FLASH
No. Of Macrocells
192
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Rohs Compliant
Yes
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
240
Number Of Macrocells
192
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Figure 3–5. UFM Erase Waveform
Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices
May 2011 Altera Corporation
t
t
t
C4
R4
LOCAL
Routing
External Timing Parameters
f
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera
OSC_ENA
Program
DRDout
DRShft
ARShft
DRDin
ARDin
DRClk
ARClk
Erase
Busy
Min
5M40Z/ 5M80Z/ 5M160Z/
C4
t
t
5M240Z/ 5M570Z
ADS
1,143
ASU
Max
860
655
t
ACLK
Table 3–32 on page 3–23
Min
9 Address Bits
C5, I5
1,973
1,479
2,947
Max
CPLDs.
t
ADH
t
AH
t
EB
t
OSCS
Min
t
through
EPMX
C4
t
OSCH
5M1270Z/ 5M2210Z
Max
561
445
731
Table 3–36 on page
t
BE
Min
C5, I5
MAX V Device Handbook
Max
690
548
899
3–25.
Unit
ps
ps
ps
3–19

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