5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 20

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2–14
MultiTrack Interconnect
MAX V Device Handbook
In the MAX V architecture, connections between LEs, the UFM, and device I/O pins
are provided by the MultiTrack interconnect structure. The MultiTrack interconnect
consists of continuous, performance-optimized routing lines used for inter- and
intra-design block connectivity. The Quartus II Compiler automatically places critical
design paths on faster interconnects to improve design performance.
The MultiTrack interconnect consists of row and column interconnects that span fixed
distances. A routing structure with fixed length resources for all devices allows
predictable and short delays between logic levels instead of large delays associated
with global or long routing lines. Dedicated row interconnects route signals to and
from LABs within the same row. These row resources include:
■
■
The DirectLink interconnect allows an LAB to drive into the local interconnect of its
left and right neighbors. The DirectLink interconnect provides fast communication
between adjacent LABs and blocks without using row interconnect resources.
The R4 interconnects span four LABs and are used for fast row connections in a
four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or
right.
can drive and be driven by row IOEs. For LAB interfacing, a primary LAB or
horizontal LAB neighbor can drive a given R4 interconnect. For R4 interconnects that
drive to the right, the primary LAB and right neighbor can drive on to the
interconnect. For R4 interconnects that drive to the left, the primary LAB and its left
neighbor can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4 interconnects can also
drive C4 interconnects for connections from one row to another.
DirectLink interconnects between LABs
R4 interconnects traversing four LABs to the right or left
Figure 2–10
shows R4 interconnect connections from an LAB. R4 interconnects
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
MultiTrack Interconnect