5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 23

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2: MAX V Architecture
Logic Elements
Figure 2–8. LE in Dynamic Arithmetic Mode
Note to
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
December 2010 Altera Corporation
LAB Carry-In
Carry-In0
Carry-In1
Figure
data1
data2
data3
(LAB Wide)
addnsub
2–8:
(1)
The other two LUTs use the data1 and data2 signals to generate two possible
carry-out signals: one for a carry of 1 and the other for a carry of 0. The carry-in0
signal acts as the carry-select for the carry-out0 output and carry-in1 acts as the
carry-select for the carry-out1 output. LEs in arithmetic mode can drive out
registered and unregistered versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable, synchronous
up/down control, synchronous clear, synchronous load, and dynamic
adder/subtractor options. The LAB local interconnect data inputs generate the
counter enable and synchronous up/down control signals. The synchronous clear
and synchronous load options are LAB-wide signals that affect all registers in the
LAB. The Quartus II software automatically places any registers that are not used by
the counter into other LABs. The addnsub LAB-wide signal controls whether the LE
acts as an adder or subtractor.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in
dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation
to increase the speed of carry functions. The LE is configured to calculate outputs for a
possible carry-in of 0 and carry-in of 1 in parallel. The carry-in0 and carry-in1
signals from a lower-order bit feed forward into the higher-order bit via the parallel
carry chain and feed into both the LUT and the next portion of the carry chain.
Carry-select chains can begin in any LE within an LAB.
Carry-Out0
LUT
LUT
LUT
LUT
Carry-Out1
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
Register Feedback
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
MAX V Device Handbook
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
2–11