LFE2M70E-5FN900C LATTICE SEMICONDUCTOR, LFE2M70E-5FN900C Datasheet - Page 159
LFE2M70E-5FN900C
Manufacturer Part Number
LFE2M70E-5FN900C
Description
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeECP2Mr
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M70E-5FN900C
No. Of Logic Blocks
67000
No. Of Macrocells
34000
No. Of Speed Grades
5
No. Of I/o's
416
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Total Ram Bits
4534Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M70E-5FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA
Number
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
W21
M10
M11
M12
M13
M15
Ball
N10
N11
N12
N13
N15
P14
P20
R10
R11
R12
R13
U17
Y14
H17
H16
H20
H18
N18
J16
W2
M8
N8
P3
P9
U6
Y9
H6
H3
H2
K6
N6
L8
J6
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Bank
LFE2-12E/12SE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Dual Function
Differential
4-59
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-20E/20SE
Dual Function
Pinout Information
Differential
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