DSPIC30F2012-30I/ML Microchip Technology, DSPIC30F2012-30I/ML Datasheet - Page 87
![IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2012-30I/ML
Manufacturer Part Number
DSPIC30F2012-30I/ML
Description
IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2012-30I/ML
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Package
28QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
12
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx12-bit
Number Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201230IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2012-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
12.0
This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 12-1
compare module.
FIGURE 12-1:
© 2010 Microchip Technology Inc.
Note:
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
OUTPUT COMPARE MODULE
From GP
Timer Module
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
depicts a block diagram of the output
TMR2<15:0
channel (1 or 2).
0
OUTPUT COMPARE MODE BLOCK DIAGRAM
Comparator
OCxRS
OCxR
TMR3<15:0>
dsPIC30F2011/2012/3012/3013
1
OCTSEL
T2P2_MATCH
0
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OC1CON and OC2CON
registers. The dsPIC30F2011/2012/3012/3013 devices
have 2 compare channels.
OCxRS and OCxR in
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
T3P3_MATCH
Mode Select
OCM<2:0>
1
Output
3
Logic
Set Flag bit
OCxIF
(1)
S
R
Q
Figure 12-1
Output
Enable
(for x = 1, 2, 3 or 4)
represent the Dual
OCFA
DS70139G-page 87
OCx