ISP1507BBS ST-Ericsson Inc, ISP1507BBS Datasheet - Page 21
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ISP1507BBS
Manufacturer Part Number
ISP1507BBS
Description
IC, TRANSCEIVER, USB OTG, 32HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1507BBS.pdf
(81 pages)
Specifications of ISP1507BBS
Usb Type
USB Transceiver
Usb Version
2.0
Data Rate
12Mbps
No. Of Ports
1
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
No. Of Pins
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1507BBSTM
Manufacturer:
SEMIKRON
Quantity:
22
9. Protocol description
CD00222689
Product data sheet
9.1 ULPI references
9.2 Power-On Reset (POR)
9.3 Power-up, reset and bus idle sequence
The following subsections describe the protocol for using the ISP1507.
The ISP1507 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0.
An internal POR is generated when REG1V8 rises above V
t
below V
voltage on REG1V8 is generated from V
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another t
drops to logic 0. If REG1V8 dips from t2 to t3 for > t
generated. If the dip at t4 to t5 is too short, that is, < t
will not react and will remain LOW.
Figure 6
On power-up, the ISP1507 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1507 deasserts DIR. The power-up time depends on the V
crystal start-up time, and PLL start-up time t
ISP1507 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1507 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1507. Before beginning USB packets, the
link must set the RESET bit in the FUNC_CTRL register (see
ISP1507. After the RESET bit is set, the ISP1507 will assert DIR until the internal reset
completes. The ISP1507 will automatically deassert DIR and clear the RESET bit when
reset has completed. After every reset, an RXCMD is sent to the link to update USB status
information. After this sequence, the ULPI bus is ready for use and the link can start USB
operations.
w(REG1V8_H)
Fig 5.
POR(trip)
shows a typical start-up sequence.
Internal power-on reset timing
t0
. The internal POR pulse will also be generated whenever REG1V8 drops
for more than t
t1
t
PORP
Rev. 04 — 20 May 2010
w(REG1V8_L)
t2
Figure 5
CC
, and then rises above V
.
startup(o)(CLOCK)
ISP1507A; ISP1507B
t3
t
PORP
shows a possible curve of REG1V8. The
w(REG1V8_L)
w(REG1V8_L)
t4
ULPI HS USB OTG transceiver
. Whenever DIR is asserted, the
POR(trip)
t5
Section
CC
, another POR pulse is
, the internal POR pulse
supply rise time, the
POR(trip)
, for at least
© ST-ERICSSON 2010. All rights reserved.
10.1.2) to reset the
004aaa751
PORP
REG1V8
V
POR
POR(trip)
again. The
before it
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