A3992SB-T Allegro Microsystems Inc, A3992SB-T Datasheet
A3992SB-T
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A3992SB-T Summary of contents
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DMOS Dual Full-Bridge Microstepping PWM Motor Driver Features and Benefits ▪ ±1 continuous output rating ▪ Low R DMOS output drivers DS(on) ▪ Short-to-ground protection ▪ Shorted load protection ▪ Optimized microstepping via six bit linear DACs ...
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... A3992 Selection Guide Part Number A3992SB-T A3992SLPTR-T Tape, 4000 pieces/reel Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Supply Voltage Logic Input Voltage Range VBBx to OUTx Voltage OUTx to SENSEx Voltage REF Reference Voltage SENSE Voltage (DC) Operating Ambient Temperature Maximum Junction Temperature ...
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A3992 VDD UVLO and Fault Detect MUX Bit Linear DAC Internal Oscillator OSC OSC Select/ Divider CLOCK DATA Serial Port STROBE SLEEP REF 6 Bit REF Buffer Linear DAC Microstepping ...
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A3992 ELECTRICAL CHARACTERISTICS 1 valid at T Characteristic Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Supply Voltage Range Logic Input Voltage Logic ...
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A3992 The A3992 is controlled via a 3 wire serial port. The programmable functions allow maximum fl exibility in confi guring the PWM to the motor drive requirements. The serial data is written as two 19 bit words, 1 bit ...
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A3992 Word 1 Bit Assignments Word 1 is selected by setting Assignments are summarized in the following table, and described in detail in the remainder of this section. Word 1 Bit Assignments Bit Function D0 Word Select ...
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A3992 D14 – D15 Synchronous Rectifi cation. different modes of operation (see Synchronous Rectifi - cation in the Functional Description section): D15 D14 Synchronous Rectifier Allegro defined use The VREG pin should ...
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A3992 Charge Pump (CP1 and CP2). used to generate a gate supply greater than V drive the source FET gates. A 0.22 μF ceramic capaci- tor is required between CP1 and CP2 for pumping purposes. A 0.22 μF ceramic capacitor ...
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A3992 When a PWM off-cycle Synchronous Rectifi cation. is triggered bridge disable command or internal fi xed off-time cycle, load current recirculates accord- ing to the decay mode selected by control logic. The A3992 synchronous rectifi cation feature ...
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A3992 Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3992 must be soldered directly onto the board. On the underside of the A3992 pack- age is an exposed pad, which provides ...
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A3992 B Package VCP 1 CP1 2 CP2 3 OUT1B 4 VBB1 5 GND 6 GND 7 SENSE1 8 OUT1A 9 STROBE 10 CLOCK 11 DATA 12 Terminal List Table Number B Package Package ...
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A3992 Package B, 24 Pin DIP with Fused Pins Package B, 24 Pin DIP with Fused Pins 1.27 MIN +0.25 1.52 –0.38 0.018 0.46 ±0.12 Microstepping PWM Motor Driver +0.25 30.10 –0.64 +0.76 +0.38 6.35 10.92 ...
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A3992 Package LP, 24 Pin TSSOP with Exposed Thermal Pad Package LP, 24 Pin TSSOP with Exposed Thermal Pad 7.80 ±0. 4.32 24X 0.10 C +0.05 0.25 0.65 –0.06 Copyright ©2006-2008, Allegro MicroSystems, Inc. The ...