PCF8574AP NXP Semiconductors, PCF8574AP Datasheet - Page 11

• Manufacturer Part Number: PCF8574AP
• Description: IC, I/O EXPANDER, 8BIT, 100KHZ, DIP-16
• Manufacturer: NXP Semiconductors

Specifications of PCF8574AP

• Chip Configuration: 8 Bit
• Bus Frequency: 100kHz
• Ic Interface Type: I2C
• No. Of I/o's: 8
• Supply Voltage Range: 2.5V To 6V
• Digital Ic Case Style: DIP
• No. Of Pins: 16
• Termination Type: SMD
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 100kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
7.2
The PCF8574 provides an open drain output (INT) which
can be fed to a corresponding input of the microcontroller.
This gives these chips a type of master function which can
initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the
port inputs in the input mode. After time t
valid.
Resetting and reactivating the interrupt circuit is achieved
when data on the port is changed to the original setting or
data is read from or written to the port which has generated
the interrupt.
Resetting occurs as follows:
1997 Apr 02
handbook, full pagewidth
handbook, full pagewidth
In the READ mode at the acknowledge bit after the rising
edge of the SCL signal
In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal
Remote 8-bit I/O expander for I
Interrupt (see Figs 12 and 13)
DATA INTO
INT
P5
SDA
SCL
t iv
MICROCOMPUTER
start condition
S
Fig.13 Interrupt generated by a change of input to I/O P5.
Fig.12 Application of multiple PCF8574s with interrupt.
0
1
slave address (PCF8574)
1
2
INT
iv
the signal INT is
0
3
0
4
V DD
2
A2
5
C-bus
A1
6
PCF8574
A0
7
11
INT
(1)
R/W acknowledge
Each change of the I/Os after resetting will be detected
and, after the next rising clock edge, will be transmitted as
INT. Reading from or writing to another device does not
affect the interrupt circuit.
7.3
A quasi-bidirectional I/O can be used as an input or output
without the use of a control signal for data direction.
At power-on the I/Os are HIGH. In this mode only a current
source to V
allows fast rising edges into heavily loaded outputs. These
devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should
be HIGH before being used as inputs.
1
8
Interrupts which occur during the acknowledge clock
pulse may be lost (or very short) due to the resetting of
the interrupt during this pulse.
A
from slave
t ir
PCF8574
Quasi-bidirectional I/Os (see Fig.14)
INT
(2)
DD
is active. An additional strong pull-up to V
P5
1
data from port
MBD976
PCF8574
(16)
INT
Product specification
PCF8574
1
condition
MBD972
stop
P
DD