CS4341-KS Cirrus Logic Inc, CS4341-KS Datasheet - Page 24

• Manufacturer Part Number: CS4341-KS
• Description: IC, DAC, 24BIT, 96KSPS, SOIC-16
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-KS

• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Data Interface: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Clock - SCLK
Reset - RST
Serial Control Interface Clock - SCL/CCLK
Serial Control Data I/O - SDA/CDIN
Address Bit / Chip Select - AD0/CS
Mute Control - MUTEC
24
Pin 3, Input
Function:
Pin 1, Input
Function:
Pin 6, Input
Function:
Pin 7, Input/Output
Function:
Pin 8, Input
Function:
Pin 16, Output
Function:
Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-26.
The CS4341 supports both internal and external serial clock generation modes. The Internal Serial Clock
Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode
is always preferred.
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master
clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data
format, as shown in Figures 20-26. Operation in this mode is identical to operation with an external serial
clock synchronized with LRCK.
External Serial Clock Mode
The CS4341 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected
on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode
if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
The device enters a low power mode and all internal registers are reset to the default settings, including
the control port, when low. When high, the control port becomes operational and the PDN bit must be
cleared before normal operation will occur. The control port can not be accessed when reset is low.
Clocks the serial control data into or from SDA/CDIN.
In I
In I
device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device
has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
2
2
C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode.
C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The
CS4341
DS298PP2