CS4341-KS Cirrus Logic Inc, CS4341-KS Datasheet - Page 23

• Manufacturer Part Number: CS4341-KS
• Description: IC, DAC, 24BIT, 96KSPS, SOIC-16
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341-KS

• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Current: 15mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Data Interface: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Master Clock - MCLK
Left/Right Clock - LRCK
Serial Audio Data - SDATA
DS298PP2
Sample Rate
* Requires MCLKDIV bit = 1 in MCLK Control Register (address 00h)
(kHz)
44.1
88.2
32
48
64
96
Pin 5, Input
Function:
Pin 4, Input
Function:
Pin 2, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base
Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note
that some multiplication factors require setting the MCLKDIV bit in the MCLK Control Register. Table 12
illustrates several standard audio sample rates and the required master clock frequencies.
The Left/Right clock determines which channel is currently being input on the serial audio data input, SDA-
TA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right
sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs
will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
Two’s complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-26.
11.2896
12.2880
4.0960
5.6448
6.1440
8.1920
128x
12.2880
16.9344
18.4320
6.1440
8.4672
9.2160
192x
HRM
12.2880
16.3840
22.5792
24.5760
11.2896
8.1920
256x*
Table 12. Common Clock Frequencies
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
384x*
MCLK (MHz)
11.2896
12.2880
8.1920
256x
-
-
-
12.2880
16.9344
18.4320
384x
-
-
-
16.3840
22.5792
24.5760
512x
BRM
-
-
-
24.5760
32.7680
36.8640
768x*
-
-
-
CS4341
32.7680
45.1584
49.1520
1024x*
-
-
-
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