WM8737LGEFL/R Wolfson Microelectronics, WM8737LGEFL/R Datasheet - Page 32

• Manufacturer Part Number: WM8737LGEFL/R
• Description: IC, ADC, 24BIT, 96KHZ, QFN-32
• Manufacturer: Wolfson Microelectronics

Specifications of WM8737LGEFL/R

• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Data Interface: 2-Wire, 3-Wire, Serial
• Supply Voltage Range - Analog: 1.8V To 3.6V
• Supply Current: 7.75mA
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8737L
REGISTER
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
w
REGISTER MAP
Table 21 Control Register Map
(BIT 15 – 9)
ADDRESS
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111 Audio Format
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
Audio Path R
Audio Path L
ADC Control
Power Mgmt
3D Enhance
Misc. biases
Mic Preamp
Noise Gate
REMARKS
Right PGA
Left PGA
Clocking
Control
control
Reset
ALC1
ALC2
ALC3
Standby mode 1 is achieved by powering down everything except the VMID source and gives a very
low power sleep mode. Wake-up may require a few milliseconds to ensure that the VREF voltage
has stabilized.
Standby mode 2 is achieved by not powering down VMID and VREF. The WM8737L can awaken
instantly from standby mode 2 because VREF is already stable.
Table 20 Power Management
R6 (06h)
Power
Manageme
nt
R2 (02h)
R3 (03h)
Notes: All control bits are 0=OFF, 1=ON
REGISTER
ADDRESS
Reserved (must write zeros)
VMID
RVU
BIT8
LVU
0
0
0
0
0
0
0
MONOMIX
ALCSEL
RESET (writing 000000000 to this register resets all registers to their default state)
RINSEL
LINSEL
8
7
6
5
4
3
2
1:0
4
4
BIT
DETECT
SDODIS
AUTO
VREF
DIV2
BIT7
0
0
0
VMID
VREF
AI
PGL
PGR
ADL
ADR
MICBIAS
LMBE
RMBE
LABEL
DCY (Decay Time)
3DLC
DIV2
CLK
BIT6
RMICBOOST
LMICBOOST
MS
AI
POLARITY
0
0
0
0
0
0
0
0
0
0
00
0
0
MAXGAIN
DEFAULT
3DUC
PGL
BIT5
0
0
0
0
0
ALCZCE
RMBE
HPOR
LMBE
SR (Sample Rate Selection)
PGR
BIT4
LRP
VMID (necessary for all other functions)
VREF (necessary for all other functions)
Audio Interface
PGA Left
PGA Right
ADC Left
ADC Right
see “Microphone Bias” section
Mic Boost Left (see “Input Signal Path”)
Mic Boost Right (see “Input Signal Path”)
RINVOL [7:0]
LINVOL [7:0]
0
0
NGTH (Threshold)
RBYPEN LBYPEN
RMZC
LMZC
ADL
BIT3
VMIDSEL [1:0]
0
3DDEPTH
WL
DESCRIPTION
ALCL (Target Level)
ATK (Attack Time)
RPZC
LPZC
HLD (Hold Time)
ADR
BIT2
LP
PD, Rev 4.1, April 2009
MONOUT
LINPUT1
ENABLE
dc BIAS
BIT1
MBCTRL[1:0]
Production Data
RZCTO[1:0]
LZCTO[1:0]
0
FORMAT
MICBIAS
RINPUT1
ENABLE
dc BIAS
NGAT
Mode
ADC
HPD
USB
3DE
BIT0
32