WM8737LGEFL/R Wolfson Microelectronics, WM8737LGEFL/R Datasheet - Page 28

• Manufacturer Part Number: WM8737LGEFL/R
• Description: IC, ADC, 24BIT, 96KHZ, QFN-32
• Manufacturer: Wolfson Microelectronics

Specifications of WM8737LGEFL/R

• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Data Interface: 2-Wire, 3-Wire, Serial
• Supply Voltage Range - Analog: 1.8V To 3.6V
• Supply Current: 7.75mA
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8737L
w
MASTER CLOCK AND AUDIO SAMPLE RATES
Table 14 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length is 24 bits.
To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT
tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have
been programmed, the audio interface can be activated under software control by setting the AI bit
(see “Power Management” section).
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8737L supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock.
There are two clocking modes:
•
•
Table 15 Clocking and Sample Rate Control
The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital
filter chacteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital
Filter Characteristics).
R8 (08h)
Clocking and
Sample Rate
Control
REGISTER
ADDRESS
REGISTER
ADDRESS
‘Normal’ mode supports master clocks of 128f
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio ADC.
4
6
7
BIT
6
0
5:1
7
BIT
LRP
MS
SDODIS
LABEL
CLKDIV2
USB
SR[4:0]
AUTO
DETECT
LABEL
0
0
0
DEFAULT
0
0
0000
0
s
DEFAULT
, 192f
s
, 256f
Right, left & I2S modes – ADCLRC
polarity
1 = invert ADCLRC polarity
0 = normal ADCLRC polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK
rising edge after ADCLRC rising edge
(mode B)
0 = MSB is available on 2nd BCLK
rising edge after ADCLRC rising edge
(mode A)
1: Master Mode
0: Slave Mode
0: ADCDAT pin enabled
1: ADCDAT pin off (high impedance)
Master / Slave Mode Control
ADCDAT serial data pin disable
s
, 384f
Master Clock Divide by 2
1: MCLK is divided by 2
0: MCLK is not divided
Clocking Mode Select
1: USB Mode
0: ‘Normal’ Mode
Sample Rate Control
Clock Ratio Autodetect
(Slave Mode Only)
0: Autodetect Off
1: Autodetect On
s
, and their multiples
DESCRIPTION
DESCRIPTION
PD, Rev 4.1, April 2009
Production Data
28