LIS3L02DQ-TR STMicroelectronics, LIS3L02DQ-TR Datasheet - Page 9

• Manufacturer Part Number: LIS3L02DQ-TR
• Description: ACCELEROMETER TRPL AXIS 44QFN
• Manufacturer: STMicroelectronics

Specifications of LIS3L02DQ-TR

• Axis: X, Y, Z
• Acceleration Range: ±2g
• Sensitivity: 1024 LSb/g
• Voltage - Supply: 2.7 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 1.5kHz
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIS3L02DQ
ing the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low
during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged
to generate an acknowledge after each byte of data has been received.
2
The I
C embedded inside the LIS3L02DQ behaves like a slave device and the following protocol must be
adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been
returned, a 8-bit sub-address will be transmitted: the 7 LSB represent the actual register address while the
MSB enables address autoincrement. If the MSB of the SUB field is 1, the SUB (register address) will be
automatically incremented to allow multiple data read/write.
If the LSB of the slave address is ‘1’ (read), a repeated START condition will have to be issued after the
two sub-address bytes; if the LSB is ‘0’ (write) the Master will transmit to the slave with direction un-
changed.
Transfer when Master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
Transfer when Master is writing multiple bytes to slave:
Master
ST
SAD + W
SUB
DATA
DATA
SP
Slave
SAK
SAK
SAK
SAK
Transfer when Master is receiving (reading) one byte of data from slave:
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
SAK
SAK
DATA
Transfer when Master is receiving (reading) multiple bytes of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
MAK
Slave
SAK
SAK
SAK
DATA
Master
SR
MAK
NMAK
SP
Slave
DATA
DATA
Data is transmitted in byte format. Each data transfer contains 8 bits. The number of bytes transferred per
transfer is unlimited. Data is transferred with the Most Significant Bit (MSB) first. If a receiver can’t receive
another complete byte of data until it has performed some other function, it can hold the clock line, SCL
LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for
another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it
is not able to receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the
SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation
of a STOP condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-address field. In
other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read.
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