LIS3DHTR STMicroelectronics, LIS3DHTR Datasheet - Page 22

• Manufacturer Part Number: LIS3DHTR
• Description: ACCELEROMETER 3AXIS MEMS 16-LGA
• Manufacturer: STMicroelectronics

Specifications of LIS3DHTR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10613-2

Digital interfaces
Table 16.
6.2
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Master ST SAD+W
Slave
Table 15.
Transfer when master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
SPI bus interface
The LIS3DH SPI is a bus slave. The SPI allows to write and read the registers of the device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 6.
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
Master
Slave
SDO
SPC
SDI
CS
SAK
ST
Transfer when master is receiving (reading) one byte of data from slave:
Read and write protocol
SAD + W
SUB
RW
SAK
MS
AD5 AD4 AD3 AD2 AD1 AD0
SAK
SR SAD+R
Doc ID 17530 Rev 1
SUB
SAK
SAK DATA
SR
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SAD + R
MAK
DATA
SAK
MAK
DATA
DATA
NMAK
NMAK SP
LIS3DH
SP