DC1241B-AA Linear Technology, DC1241B-AA Datasheet - Page 23

• Manufacturer Part Number: DC1241B-AA
• Description: BOARD EVAL LTM9001-AA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1241B-AA

• Design Resources: DC1241B Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9001 16bit Receiver Subsystem, 162MHz BPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9001
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

APPLICATIONS INFORMATION
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTM9001 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF . A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 11 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT
versa, which creates a ±350mV differential voltage across
the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.2V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
resistor, even if the signal is not used (such as OF
CLKOUT
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
+
/CLKOUT
DD
voltages will also help reduce interference
–
). To minimize noise the PC board
LATCH
LTM9001
FROM
DATA
PREDRIVER
LOGIC
V
DD
Figure 11. Equivalent Output Buffer in LVDS Mode
+
to OUT
10k
+
1.20V
–
/OF
or vice
V
DD
–
or
+
–
3.5mA
10k
In low power LVDS mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output common
mode voltage is 1.2V, the same as standard LVDS mode.
Data Format
The LTM9001 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3V
external resistive divider can be used to set the 1/3V
and 2/3V
for the MODE pin.
Table 5. MODE Pin Function
Overfl ow Bit
An overfl ow output bit (OF) indicates when the converter is
overranged or underranged. In CMOS mode, a logic high on
the OFA pin indicates an overfl ow or underfl ow on the A data
bus, while a logic high on the OFB pin indicates an overfl ow
on the B data bus. In LVDS mode, a differential logic high
on OF
0V(GND)
1/3V
2/3V
MODE
V
OV
DD
DD
DD
+
DD
LTM9001-Ax/LTM9001-Bx
/OF
OV
DD
DD
–
OUTPUT FORMAT
pins indicates an overfl ow or underfl ow.
43Ω
43Ω
2’s Complement
2’s Complement
logic levels. Table 5 shows the logic states
Offset Binary
Offset Binary
9001 F11
100Ω
OGND
OV
3.3V
DD
RECEIVER
LVDS
CLOCK DUTY CYCLE STABILIZER
DD
, 2/3V
DD
Off
On
On
Off
and V
23
DD
. An
9001fc
DD