DC1241B-AA Linear Technology, DC1241B-AA Datasheet - Page 14

• Manufacturer Part Number: DC1241B-AA
• Description: BOARD EVAL LTM9001-AA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1241B-AA

• Design Resources: DC1241B Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9001 16bit Receiver Subsystem, 162MHz BPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9001
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9001-Ax/LTM9001-Bx
PIN FUNCTIONS
Supply Pins
V
The voltage on this pin provides power for the amplifi er
stage only and is internally bypassed to GND.
V
supply is internally bypassed to GND.
OV
Drivers. This supply is internally bypassed to OGND.
GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1,
F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground.
OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground.
Analog Inputs
IN
IN
DNC (Pins C3, D3): Do Not Connect. These pins are used
for testing and should not be connected on the PCB. They
may be soldered to unconnected pads and should be well
isolated. The DNC pins connect to the signal path prior to
the ADC inputs; therefore, care should be taken to keep
other signals away from these sensitive nodes.
ENC
sampled analog input is held on the rising edge of ENC
This input is internally biased to 1.6V through a 6.2k
resistor. Output data can be latched on the rising edge
of ENC
impedance.
ENC
sampled analog input is held on the falling edge of ENC
This input is internally biased to 1.6V through a 6.2k resistor.
Bypass to ground with a 0.1μF capacitor for a single-ended
encode signal. The encode pins have a differential 100Ω
input impedance.
Control Inputs
SENSE (Pin J3): Reference Mode Select and External
Reference Input. Tie SENSE to V
2.5V bandgap reference. An external reference of 2.5V
or 1.25V may be used; both reference values will set the
maximum full-scale input range.
14
CC
DD
+
–
DD
(Pin G1): Positive (Non-Inverting) Amplifi er Input.
(Pin H1): Negative (Inverting) Amplifi er Input.
(Pins E1, E2): 3.3V Analog Supply Pin for Amplifi er.
+
(Pins E5, D5): 3.3V Analog Supply Pin for ADC. This
–
(Pins A6, G9): Positive Supply for the ADC Output
(Pin C1): Positive Differential Encode Input. The
(Pin B1): Negative Differential Encode Input. The
+
. The Encode pins have a differential 100Ω input
DD
to select the internal
+
–
.
.
AMPSHDN (Pin H3): Power Shutdown Pin for Amplifi er.
This pin is a logic input referenced to analog ground.
AMPSHDN = low results in normal operation. AMPSHDN
= high results in powered down amplifi er with typically
3mA amplifi er supply current.
MODE (Pin G3): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty cycle
stabilizer. Connecting MODE to 1/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
RAND (Pin F3): Digital Output Randomization Selection
Pin. RAND = low results in normal operation. RAND =
high selects D1 to D15 to be EXCLUSIVE-ORed with D0
(the LSB). The output can be decoded by again applying
an XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin E3): Programmable Gain Amplifi er Control Pin.
PGA = low selects the normal (maximum) input voltage
range. PGA = high selects a 3.5dB reduced input range
for slightly better distortion performance at the expense
of SNR.
ADCSHDN (Pin B3): Power Shutdown Pin for ADC.
ADCSHDN = low results in normal operation. ADCSHDN
= high results in powered down analog circuitry and the
digital outputs are placed in a high impedance state.
DITH (Pin A3): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
LVDS (Pin F5): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3V
LVDS to 2/3V
LVDS to V
DD
selects demultiplexed CMOS mode. Connecting
DD
DD
selects standard LVDS mode.
selects low power LVDS mode. Connecting
DD
selects 2’s complement output
DD
selects 2’s complement
DD
selects offset binary
9001fc