EVAL-ADF7012DBZ4 Analog Devices Inc, EVAL-ADF7012DBZ4 Datasheet - Page 12

• Manufacturer Part Number: EVAL-ADF7012DBZ4
• Description: BOARD EVALUATION DB4 FOR ADF7012
• Manufacturer: Analog Devices Inc
• Type: Transmitterr

Specifications of EVAL-ADF7012DBZ4

• Frequency: 1GHz
• For Use With/related Products: ADF7012
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7012
CIRCUIT DESCRIPTION
PLL OPERATION
A fractional-N PLL allows multiple output frequencies to be
generated from a single-reference oscillator (usually a crystal)
simply by changing the programmable N value found in the
N register. At the phase frequency detector (PFD), the reference
is compared to a divided-down version of the output frequency
(VCO/N). If VCO/N is too low a frequency, typically the output
frequency is lower than desired, and the PFD and charge-pump
combination sends additional current pulses to the loop filter.
This increases the voltage applied to the input of the VCO.
Because the VCO of the ADF7012 has a positive frequency vs.
voltage characteristic, any increase in the V
to the VCO input increases the output frequency at a rate of
kilovolts, the tuning sensitivity of the VCO (MHz/V). At each
interval of 1/PFD seconds, a comparison is made at the PFD
until the PFD and charge pump eventually force a state of
equilibrium in the PLL where PFD frequency = VCO/N. At
this point, the PLL can be described as locked.
For a fractional-N PLL
where N
CRYSTAL OSCILLATOR
The on-board crystal oscillator circuitry (Figure 27) allows an
inexpensive quartz crystal to be used as the PLL reference. The
oscillator circuit is enabled by setting XOEB low. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the error correction
register within the R register.
A single-ended reference may be used instead of a crystal, by
applying a square wave to the OSC2 pin, with XOEB set high.
F
F
OUT
OUT
FRAC
VCO/N
=
=
can be Bits M1 to M12 in the fractional-N register.
F
F
CRYSTAL/R
R
PFD
CRYSTAL
×
R
PFD
⎛
⎜
⎝
Figure 26. Fractional-N PLL
N
×
INT
N
CP
=
+
F
N
PFD
2
FRAC
12
LOOP FILTER
N
×
N
⎞
⎟
⎠
TUNE
VCO
voltage applied
FVCO
(1)
(2)
Rev. A | Page 12 of 28
Two parallel resonant capacitors are required for oscillation at
the correct frequency—the value of these depend on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds to give the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary between 2 pF to 5 pF, depending on board layout.
Where possible, to ensure stable frequency operation over all
conditions, capacitors should be chosen so that they have a
very low temperature coefficient and/or opposite temperature
coefficients
Typically, for a 10 MHz crystal with 20 pF load capacitance,
the oscillator circuit can tolerate a crystal ESR value of ≤ 50 Ω.
The ESR tolerance of the ADF7012 decreases as crystal fre-
quency increases, but this can be offset by using a crystal with
lower load capacitance.
CRYSTAL COMPENSATION REGISTER
The ADF7012 features a 15-bit fixed modulus, which allows the
output frequency to be adjusted in steps of FPFD/15. This fine
resolution can be used to easily compensate for initial error and
temperature drift in the reference crystal.
where:
F
FEC = Bit F1 to Bit F11 in the R Register
Note that the notation is twos complement, so F11 represents
the sign of the FEC number.
Example
F
F
F
FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =
11111011100 = 0x7DC
CLOCK OUT CIRCUIT
The clock out circuit takes the reference clock signal from the
Crystal Oscillator section and supplies a divided-down 50:50
mark-space signal to the CLK
2 to 30 is available. This divide is set by the DB[19:22] in the
R register. On power-up, the CLK
STEP
PFD
ADJUST
STEP
= 10 MHz
F
= 10 MHz/2
= FPFD/215
ADJUST
= −11 kHz
= F
Figure 27. Oscillator Circuit on the ADF7012
OSC1
STEP
15
× FEC
= 305.176 Hz
CP2
OUT
CP1
OSC2
pin. An even divide from
OUT
defaults to divide by 16.
(3)