ISL6558EVAL1Z Intersil, ISL6558EVAL1Z Datasheet - Page 8

• Manufacturer Part Number: ISL6558EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6558
• Manufacturer: Intersil

Specifications of ISL6558EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thus, the total power dissipated in each lower MOSFET is
approximated by the summation of Equations 26 and 27,
as P
N-phase converter is N times P
UPPER MOSFET POWER CALCULATION
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching
times; the lower-MOSFET body-diode reverse-recovery
charge, Q
loss. A large portion of the upper-MOSFET losses is due
to currents conducted across the input voltage (V
during switching intervals.
When the upper MOSFET turns off, the lower MOSFET
does not conduct any portion of the inductor current until
the voltage at the phase node falls below ground. Once
the lower MOSFET begins conducting, the current in the
upper MOSFET falls to zero as the current in the lower
MOSFET ramps up to assume the full inductor current. In
Equation 29, the required time for this commutation is t
and the associated power loss is P
Similarly, the upper MOSFET begins conducting as soon
as it begins turning on. In Equation 30, this transition
occurs over a time t
is P
A third component involves the lower MOSFET’s
reverse-recovery charge, Q
has fully commutated to the upper MOSFET before the
lower-MOSFET’s body diode can recover all of Q
conducted through the upper MOSFET across V
power dissipated is simply that in Equation 31:
Finally, the resistive part of the upper MOSFETs is given
in Equation 32 as P
P
P
P
P
P
P
UP 2 ,
UP 3 ,
LOW
LOW 2 ,
UP 1 ,
UP,2
UP 4 ,
LOW
where
≈
≈
=
.
=
=
. The overall lower MOSFETs’ power losses in an
V
V
V
=
IN
P
rr
IN
R
IN
I
LOW 1
Q1 RMS
; and the upper MOSFET r
Q1
V
•
•
D ON
•
⎛
⎝
,
⎛
⎝
(
Io
---- -
•
Q
N
Io
---- -
N
,
I
rr
Q1 RMS
2
–
+
+
)
•
I
---------------- -
I
---------------- -
Lo PP
,
•
P
Fsw
Lo PP
=
UP,4
Fsw
2
LOW 2
,
2
2
,
, and the approximate power loss
⎞
⎠
⎛ ⎞
⎝ ⎠
.
⎞
⎠
,
•
Io
---- -
N
•
•
⎛ ⎞
⎝ ⎠
⎛
⎜
⎝
⎛ ⎞
⎝ ⎠
t
----
2
2
Io
---- -
t
----
2
N
2
8
1
rr
+
+
. Since the inductor current
•
I
----------------- -
•
Lo PP
2
Fsw
I
-------- -
LOW
Fsw
12
PP
2
,
⎞
⎟
⎠
UP,1
t
.
d1
•
DS(ON)
D
+
.
⎛
⎜
⎝
Io
---- -
N
Application Note 1029
–
I
-------- -
PP
2
conduction
⎞
⎟
⎠
(EQ. 28)
(EQ. 29)
(EQ. 31)
(EQ. 32)
IN
(EQ. 30)
t
(EQ. 27)
rr
d2
IN
, it is
. The
)
1
where R
The total power dissipated in each upper MOSFET can
now be approximated as the summation of Equations 29
through 32, as P
losses in an N-phase converter is N times P
DRIVER LOSSES CALCULATION
The driver losses due to the gate charge (Qg) of the
MOSFETs should be investigated thoroughly to prevent
over stressing, especially in high-switching frequency
applications. The switching losses of each-channel driver
and its corresponding average driver current due to the
gate charge can be estimated with Equations 34 and 35,
respectively:
where Qg1, Qg2 and V
MOSFET datasheet and V
voltages for both upper and lower FETs, respectively.
CONTROL LOOP DESIGN
The overall system can be considered as N voltage-mode
buck converters with/without droop in parallel and
synchronized operation. The current loop is used to
balance currents among all active channels and
determine the droop, and it is a slower loop, compared to
the voltage loop. Thus, the system can be simplified as
shown in Figure 9, for setting up an initial feedback
compensation. Equation 36 defines the approximate
open-loop transfer function.
Note that the droop loop is not accounted in Equation 36;
however, it can be included in the PSpice simulation as
shown in Figure 9.
Possible tune-up might be required for and optimum loop
response with a tool such as a Venerable system. Refer
to the ISL6557A data sheet [4] for a detailed discussion.
P
I
Ho S
DR
P
DR
UP
( )
=
=
=
⎛
⎜
⎝
=
⎛
⎜
⎝
Qg1 V
----------------------------------------
Qg1 V
---------------------------------------- -
Q1
P
G H
UP 1
•
V
is the on resistance of the upper MOSFET.
•
,
V
•
GS1
GS1
e S
+
DR_UP
( )
DR_UP
2
P
UP
UP 2
•
. The overall upper MOSFETs’ power
,
-------------------------------------------
Z
+
LO
+
+
Qg2 V
-------------------------------------------- -
Qg2 V
---------------------------------------------
( )
P
GS1,
Zo S
S
UP 3
B_UP
( )
•
+
V
,
•
V
Zo S
GS2
V
GS2
DR_LOW
+
GS2
2
DR_LOW
( )
P
and V
UP 4
are defined in the
,
⎞
⎟
⎠
B_LOW
⎞
⎟
⎠
•
•
Fsw
Fsw
UP
are drive
.
(EQ. 34)
(EQ. 35)
(EQ. 36)
July 31, 2009
(EQ. 33)
AN1029.3