ISL6558EVAL1Z Intersil, ISL6558EVAL1Z Datasheet - Page 6

• Manufacturer Part Number: ISL6558EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6558
• Manufacturer: Intersil

Specifications of ISL6558EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ESL of a capacitor is not usually listed in databooks.
It can be practically approximated with Equation 11:
where F
lowest impedance of the capacitor. The dV
Equation 10 is usually filtered out with low ESR ceramic
capacitors.
At the very edge of the transient, the equivalent ESL of
all output capacitors induces a spike, as defined in
Equation 12 for a given dI/dt, that adds on the top of the
existing voltage dip/overshoot due to the effective ESR
and capacitance of output capacitors.
Thus, the overall load transient can be conservatively
approximated with Equation 13, in which the last term
can be normally dropped out if the very edge of the
transient is the dominant peak, as shown in Figure 6.
The last term in Equation 13 is a direct consequence of
the amount of output capacitance. After the initial spike,
all the excessive charge is dumped into the output
capacitors on step-down transients causing a temporary
ESL
ΔV
Δ
V
Vo
f(Istep)
ESL
where
TRAN
=
ΔV
------- -
Co
=
f Istep
1
f Istep
Δ
RES
ESL
f Istep
Δ
f
(
≈
(
(
c
V
V
ESL
f Istep
•
= System Closed-Loop Bandwidth
CAP
(
CAP
FIGURE 6. TRANSIENT RESPONSE
----------------------------------- -
(
Td
2π F
is the resonant frequency that produces the
•
)
) Istep ESR
)
•
=
dI
---- -
dt
≈
≈
=
=
)
1
------------------------------ -
2π f
Δ
Δ
+
RES
Istep
dTp
V
V
ΔV
Istep
HUMP
•
SAG
)
c
ESL
•
2
----------------------------------------------------------------------- -
•
1
Co
+
+
Δ
(
2π f
6
V
2π f
for
CAP
for
for
for
•
•
c
ΔV
Istep
•
c
CAP
Co ESR
•
step-down transients
step-up transients
Co
fc
fc
•
»
«
--------------------------------------- -
2π ESR
--------------------------------------- -
2π ESR
•
Application Note 1029
•
ESL
)
2
1
1
(EQ. 11)
(EQ. 12)
(EQ. 13)
term in
•
•
Co
Co
hump at the output; the output capacitors deliver extra
charge to meet the load demand on step-up transients
causing a temporary sag before the output inductors
catch the load. The approximate response time intervals
for removal and application of a transient load are
defined by dTn and dTp, respectively, plus Td contributed
by the propagation delay of the error amplifier of the
controller. The critical inductances (Lcr1 and Lcr2) are
the largest inductance that gives the fastest responses
for step-down and step-up load transients, respectively
[6].
INPUT FILTER DESIGN
Another benefit of the interleaved approach is to reduce
the input ripple current. Input capacitance is determined
in part by the maximum input ripple current. Multi-phase
topologies can improve overall system cost and size by
lowering the input ripple current and allowing the
designer to reduce the cost of input capacitors. Equation
16 defines the RMS value of the ripple current through
the input capacitors, where the K
capacitor RMS current multiplier with respect to the
output current, and the K
RMS current multiplier with respect to the inductor
current ramp. Figures 7 and 8 plot these multipliers verse
the duty cycle.
K
I
ΔV
K
ΔV
IN RMS
RAMP CM
IN CM
,
SAG
HUMP
where
where
,
,
≈
=
=
Istep
----------------------------------------------------- -
≈
Istep
----------------------------------------------------- -
=
(
--------------------------------------------------------------------------- -
K
N D
IN CM
2
dTp
•
•
m
----------------------------------------------------------------------------------------------------------------- -
Lcr2
dTp
V
2 Co
,
(
•
2
3
dTp
•
Lcr1
2 Co
(
–
(
dTn
N D
=
dTn
dTn
•
=
m
≈
•
•
=
V
+
------------------------------------------------------ -
N V
------- -
4f
Io
+
1
2
=
2Td
N V
--------------------------------------------------- -
+
=
≈
c
2
•
1
N
–
–
)
•
+
2Td
------- -
4f
--------------------------------- -
4 I • step f
2
Io
---- - R
Istep L
-----------------------
m
N
1
4 I • step f •
•
3
RAMP,CM
K
N V
Istep L
c
)
(
N V1
•
+
•
RAMP CM
2
•
m N D
•
)
(
1
•
(
Dmax D
Dmax D
–
12N
)
Q1
•
1
3
•
+
,
•
•
2
(
IN,CM
m 1
D
c
–
is the input-capacitor
c
–
)
2
–
•
I
)
)
Lo PP
2
)
2
is the input-
,
(
for
for
m N D
for
for
–
L
L
L
L
•
≥
≥
(EQ. 15)
(EQ. 14)
<
<
July 31, 2009
Lcr1
Lcr2
(EQ. 17)
(EQ. 16)
(EQ. 18)
Lcr1
Lcr2
)
3
AN1029.3