ISL6420BEVAL1Z Intersil, ISL6420BEVAL1Z Datasheet - Page 17

• Manufacturer Part Number: ISL6420BEVAL1Z
• Description: EVAL BOARD 1 FOR ISL6420B
• Manufacturer: Intersil

Specifications of ISL6420BEVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 17. VOLTAGE - MODE BUCK CONVERTER
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6420B) and the impedance networks
Z
provide a closed loop transfer function with the highest
0dB crossing frequency (f
margin. Phase margin is the difference between the
closed loop phase at f
equations relate the compensation network’s poles, zeros
and gain to the components (R
in Figure 17. Use the following guidelines for locating the
poles and zeros of the compensation network.
F
F
IN
ΔV
LC
ESR
and Z
OSC
=
=
-------------------------------------- -
2π
OSC
-------------------------------------------- -
2π
•
FB
COMPARATOR
•
. The goal of the compensation network is to
L
COMPENSATION DESIGN
(
1
DETAILED COMPENSATION COMPONENTS
ERROR
AMP
ESR C
O
V
ISL6420B
E/A
PWM
1
•
C
Z
+
-
•
V
COMP
O
+
FB
-
C
OUT
1
O
REFERENCE
)
0dB
C
=
+
2
-
R
V
0dB
DRIVER
17
DRIVER
and 180°. The following
Z
2
REF
REF
IN
) and adequate phase
Z
×
1
FB
FB
, R
⎛
⎜
⎝
1
VIN
+
2
PHASE
R
, R
(PARASITIC)
R
------ -
R
C
4
1
4
3
⎞
⎟
⎠
3
Z
L
, C
IN
O
R
ESR
R
1
1
3
, C
C
V
O
OUT
2
, and C
V
(EQ. 4)
(EQ. 5)
OUT
ISL6420B
3
)
Compensation Break Frequency Equations
Figure 18 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the
output filter and is not shown in Figure 18. Using the
previously mentioned guidelines should give a
Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
capabilities of the error amplifier. The Loop Gain is
constructed on the log-log graph of Figure 18 by adding
the Modulator Gain (in dB) to the Compensation Gain (in
dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function
and plotting the gain.
FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop
7. Estimate Phase Margin - Repeat if Necessary
100
F
F
F
F
-20
-40
-60
80
60
40
20
Z1
P1
Z2
P2
0
(~75% F
Gain
=
=
=
=
(R2/R1)
10
20LOG
----------------------------------
2π R3 C3
----------------------------------
2π R
------------------------------------------------------ -
2π R2
----------------------------------------------------- -
2π
MODULATOR
•
•
•
•
ST
ND
ST
ND
(
1
R1
100
1
GAIN
2 C1
LC
•
Zero Below Filter’s Double Pole
Pole at the ESR Zero
•
•
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
GAIN
+
)
1
1
⎛
⎝
--------------------- -
C1
R3
C1 C2
) C3
1k
•
+
F
•
Z1
C2
FREQUENCY (Hz)
F
LC
F
⎞
⎠
Z2
10k
F
(VIN/
P1
F
ESR
100k
20LOG
F
P2
Δ
V
OSC
OPEN LOOP
ERROR AMP GAIN
1M
P2
)
COMPENSATION
GAIN
with the
CLOSED LOOP
GAIN
December 4, 2009
10M
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)
FN6901.1