LMH1982SQEEVAL/NOPB National Semiconductor, LMH1982SQEEVAL/NOPB Datasheet - Page 3

• Manufacturer Part Number: LMH1982SQEEVAL/NOPB
• Description: EVAL BOARD FOR LMH1982SQE
• Manufacturer: National Semiconductor

Specifications of LMH1982SQEEVAL/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3 REFERENCE PORTS
The LMH1982 has two reference ports (REF_A and REF_B)
with H sync and V sync inputs, which are used for phase
locking the outputs in Genlock mode. The input signals can
be measured at test points TP27, TP28, TP30, and TP31.
1.3.1 Analog Reference Input
An SD or HD analog video signal can be applied to the BNC
connector (J2) to extract H and V sync signals using the
LMH1981 (U4) or LMH1980 (U3) video sync separator. The
board is originally populated with the LMH1981, while the op-
tion for LMH1980 is not populated (NP) since the sync sepa-
rators share common application circuitry. A shunt can be
placed on jumper JP4 to enable the low-pass chroma filter,
formed by R24 and C39, to attenuate the subcarrier signal on
a composite video input.
The LMH1981 supports any SMPTE-standard SD and HD
analog video input with automatic format detection and out-
puts a low-jitter H sync signal using 50% sync slicing. The
LMH1980 can also support any SD/HD standards with auto-
matic format detection, but instead uses a fixed-level sync
slicing. Refer to the LMH1981 and LMH1980 datasheets for
more information.
The sync separator's output H and V sync signals can be
passed to port REF_A of the LMH1982 through the
NC7WZ125 (U7) logic buffer. See Table 3 for the toggle
switch definition for SW2, which controls the operation of the
U7 buffer.
1.3.2 Digital Reference Input
In addition to the analog timing signals from the sync sepa-
rator, external H and V sync input signals can be applied to
ports REF_A or REF_B via header J8. See Table 4 for the pin
assignment of J8. Note: Before applying external signals to
HIN_A and VIN_A, set SW2 = ON to avoid signal conflict with
the LMH1981.
The external reference can have digital timing, such as from
an SDI receiver or deserializer, and should be a recognized
timing format listed in Table 3 of the LMH1982 datasheet. A
48 kHz audio clock can also be applied to the H sync input to
synchronize the output clocks.
Note: The H input frequency accuracy should be within the
absolute pull range (APR) of the 27 MHz VCXO (e.g. ±50
ppm) in order to phase lock the outputs to the input reference;
otherwise, phase lock may not be achieved.
— U7 buffer output is in Hi-Z
— LMH1981 sync signals is
— External input signals can
mode
gated off from port REF_A
be applied to HIN_A and
VIN_A of header J8
Pin #
1
2
3
4
TABLE 3. Input Select Switch, SW2
ON
TABLE 4. Input Header, J8
Pin Name
GND
GND
GND
GND
— U7 buffer output is
— LMH1981 sync signals
enabled
are passed to port REF_A
Pin #
8
7
6
5
OFF
Pin Name
HIN_A
HIN_B
VIN_A
VIN_B
3
1.4 OUTPUT CLOCKS
The LVDS output SD and HD clocks from the LMH1982 are
routed via controlled 100Ω differential impedance lines to
edge-mount SMA connectors as indicated in Table 5. If a dif-
ferential probe will be used to measure the clocks directly on
the board, then the differential lines should be terminated by
populating R37 and R38 with 100Ω. If the SMA connectors
will be used to transmit the clock signal, these resistors should
not be populated; and termination should be done at the re-
ceiver instead.
To provide compatibility between various differential signaling
levels and receivers, the board allows for AC coupling capac-
itors C31/C34 and C35/C37 on the SD_CLK and HD_CLK
differential pairs. AC coupling allows for common-mode level
translation/shifting at the receiver.
1.5 OUTPUT TOP OF FRAME
The output top of frame (TOF) pulse from the LMH1982 can
be measured at test point TP23 and at header J10 located at
the bottom edge of the board. The TOF output is a 3.3V LVC-
MOS signal. The total load capacitance on the TOF output
should be less than 15 pF.
1.6 27 MHZ VCXO AND LOOP FILTER
The LMH1982 requires an external 27 MHz VCXO (X1) and
loop filter circuitry for operation of the VCXO PLL. The board
is populated with a CTS 357-series 27.0000 MHz VCXO with
±50 ppm absolute pull range (APR), which yields 1000 Hz/V
nominal tuning sensitivity (K
voltage can be measured at test point TP21.
The second-order loop filter consists of R
= 44 μF (C10 = C27 = 22 μF), and C
allel combination of C10 and C27 form the series capacitor,
C
LMH1982 datasheet, this loop filter yields a nominal -3 dB
loop bandwidth (BW) of about 3 Hz and nominal damping
factor of 0.8 assuming K
(charge pump current for PLL 1), and FB_DIV = 1716 (feed-
back divider for NTSC input). This loop filter was chosen to
give good output jitter performance when the LMH1982 is
genlocked to a clean black burst or tri-level sync reference,
such as from a Tektronix TG700 video generator.
It is possible to use different loop filter component values (or
topologies) to meet output clock jitter and lock time require-
ments for other input reference signals and applications. For
example, to generate low-jitter output clock from a high-jitter
input reference (e.g. recovered H signal from an FPGA SDI
receiver), a narrowband loop filter (e.g. BW < 1 Hz ) is rec-
ommended for maximum jitter attenuation. In addition to
changing the loop filter components, I
grammed to adjust the loop bandwidth. Refer to the LMH1982
datasheet for more complete descriptions about designing
the loop filter and optimizing the VCXO PLL loop response.
The PCB layout of the external VCXO PLL circuitry is shown
in .
S
. Based on the loop response equations provided in the
LVDS SMA Port
TABLE 5. LVDS Output Clock Ports, J3 – J6
J3 / J4
J5 / J6
VCO
VCO
= 1000 Hz/V, I
). The VCXO input control
HD_CLK / HD_CLK
SD_CLK / SD_CLK
Clock Port Name
P
= 1 μF (C28). The par-
CP1
S
= 20 kΩ (R8), C
can also be pro-
CP1
www.national.com
= 250 μA
S